| dc.description.abstract | To boost the performance of the transistor for improving the human’s life, change the channel material is imperative definitely. Among the possible materials for the replacement of the Si channel, Ge is particularly attractive due to the high mobility for both electrons and holes. Most importantly Ge is compatible with the current CMOS technology. However, the challenge for the realization of the Ge MOS devices lies in the growth of high-quality Ge on Si with sufficiently low defect densities as well as the formation of gate dielectric on Ge with satisfactory interfacial and electrical properties, both of which are incredibly challenging. Furthermore, the low dopant activation efficiency, high dopant diffusivity, and the Fermi-level pinning lead to the realization for the Ge n-MOSFET is much more difficult than Ge p-MOSFET. Our group had successfully demonstrated unique self-assembly, gate-stack heterostructure of Ge nanosphere/SiO2/Si1-xGex nanosheet on the top of Si substrate using a one-step oxidation process. Base on this result, this thesis purpose a local, high Ge contents Si1-xGex nanosheet structure to achieve the high-performance Si1-xGex n-MOSFET.
In order to fabricate the Ge nanosphere/SiO2/Si1-xGex nanosheet MOSFET, this thesis has discussed the geometrical size control for the growing oxide formed by Si1-yGey nano-pillar oxidation, and the tunability for the heterostructure of Ge nanosphere/SiO2/Si1-xGex. Size-tunable strain engineering for the tensile strains of 0.75%–3.2% and compressive strain of 0.7%–4.5% have been demonstrated for the Ge nanocrystals embedded within the SiO2 and Si3N4 respectively. The crystalline distortions are observed in both strain states as evidenced by measurements of the Grüneisen parameters, anharmonic parameters, and lattice spacings through the selective area diffraction patterns. The intervening SiO2 thickness of 2.5nm–4.5nm and Si1-xGex nanosheet thickness of 2.3nm–22.5nm are successfully tailored by the penetration depth of the Ge nanosphere within the Si substrate. Furthermore, the crystalline orientation of the Si1-xGex nanosheet appears to inherit the original crystal orientation of these Si layers. Single-crystalline (100) Si1-xGex channels with Ge content as high as x = 0.85 and a compressive strain of 3% were successfully demonstrated. Additionally, (110) Si1-xGex channels with Ge content as high as x = 0.35 with a corresponding compressive strain of 1.5% were shown to be feasible.
Armed with these techniques, this thesis has successfully fabricated and characterized the Si0.15Ge0.85 junctionless n-MOSFETs comprising a gate-stacking heterostructure of Ge-nanospherical gate/SiO2/Si0.15Ge0.85-nanosheet on SOI (100) substrate in a self-organization approach. No surface treatments before the gate-dielectrics deposition nor additional processes following gate-stack formation are needed for our Ge nanosphere/SiO2/Si1-xGex nanosheet gate-stacking structure. Superior gate modulation is evidenced by subthreshold slope of 150mV/dec and ION/IOFF > 5×108 (IOFF < 10-6 uA/um and ION > 500 uA/um) measured at VG = +1V, VD = +1V, and T = 80K for our device with channel length of 75nm. The calculated mobility reaches as high as 312.84 cm2/V·s. Device detail properties such as S/D resistance, extrinsic and intrinsic transconductance, as well as transconductance efficiency are also discussed in this thesis. | en_US |