| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 吳凱勛 | zh_TW |
| DC.creator | Kai-Xun Wu | en_US |
| dc.date.accessioned | 2016-5-6T07:39:07Z | |
| dc.date.available | 2016-5-6T07:39:07Z | |
| dc.date.issued | 2016 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:444/thesis/view_etd.asp?URN=102521013 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 隨著半導體製程的不斷進步，晶片上元件尺寸與導線寬度也逐漸的微縮，這樣的改變，使得元件之間的參數變異和不匹配關係加劇，也引進了許多難以控制的製程變動問題。在現今的類比積體電路中，電路的效能受到元件間的參數變異之影響，而元件的參數值又隨著各種不匹配的效應而改變。因此，如果想使電路產生預期的理想效能表現，就必須妥善的處理電路中的不匹配。
本論文模擬了對於電容元件各種不匹配的處理方法，從相關係數的角度出發，利用元件的空間相關特性，評估電容擺放的好壞，接著模擬了線性梯度效應、氧化層梯度效應、CMP效應和溫度的梯度效應，可根據想抵制的效應進行更有效率的擺放，這樣就可以達到較完美的抗系統變異電容陣列，最後在加上隨機性的不匹配效應，透過Monte Carlo method產生出均勻分佈的隨機亂數，將系統變異和隨機變異都考量之後，可模擬出更接近真實的效應，進而提升電路的良率。 | zh_TW |
| dc.description.abstract |
As the evolution of semiconductor process technology, the size of elements and the width of wires on chips are reduced. These changes result in some uncontrollable alterations of process and aggravate the mismatch and parameter variation of components. Nowadays, the performance of analog integrated circuits is influenced not only by the parameter variation of components but also by the mismatching effects. That is to say, the approach of mismatch effects becomes a critical issue for better anticipated performance.
This thesis simulated a method for improving mismatch of elements. In this method, we estimate capacitance placement by spatial correlation. Then simulated linear gradient、oxide gradient、CMP effect and temperature gradient, according to effect users want to resist to make effective placement, it will arrive to perfect capacitor array for resist of systematic variation. Finally, adding random mismatch, through Monte Carlo method generate uniformly random distributed variable, we could get truly approaching effect after considering systematic variation and random variation, and then improving yield of circuit. | en_US |
| DC.subject | 電容陣列區塊 | zh_TW |
| DC.subject | 系統變異分析 | zh_TW |
| DC.subject | Array Block Capacitances | en_US |
| DC.subject | Systematic Variation Analysis | en_US |
| DC.title | 應用於類比積體電路中的電容陣列區塊之系統變異分析 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Systematic Variation Analysis for Application of Array Block Capacitances in Analog Integrated Circuits | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |