博碩士論文 103323036 完整後設資料紀錄

DC 欄位	值	語言
DC.contributor	機械工程學系	zh_TW
DC.creator	李牧民	zh_TW
DC.creator	Mu-Ming Lee	en_US
dc.date.accessioned	2016-7-1T07:39:07Z
dc.date.available	2016-7-1T07:39:07Z
dc.date.issued	2016
dc.identifier.uri	http://ir.lib.ncu.edu.tw:444/thesis/view_etd.asp?URN=103323036
dc.contributor.department	機械工程學系	zh_TW
DC.description	國立中央大學	zh_TW
DC.description	National Central University	en_US
dc.description.abstract	本論文呈現的是一個針對三維集成，包含三維集成封裝、 三維集成電路，以及使用矽穿孔技術的三維集成電路之深入探 討研究報告。三維集成、封裝、三維集成電路以及矽穿孔等將 在本研究中被定義，二維集成電路到三維集成電路的演化過程 將被詳細說明，而整個三維集成電路和矽穿孔技術的架構和 製程過程也都將在此論文中詳細呈現。本論文也將針對三維集 成電路最重要核心結構的中介層做出詳細定義，也將針對中介 層的完整製程流程做說明。最後，三維集成電路之檢測機制， 應用範圍以及三維集成電路所將面臨之挑戰也被討論。	zh_TW
dc.description.abstract	This thesis presents a survey of 3D integration, including 3D IC packing, 3D IC integration and also a survey of 3D Integrated Circuits using Through Silicon Vias (TSV). 3D integration, packing, 3D IC Integrated Circuits and also TSV will be defined, the evolution of 2D IC’s to 3D IC’s and the rationale for moving to these systems will be given, and a whole overview of the construction and process of the 3D Integrated Circuit and TSV will be presented. This thesis also will give a detail caption about the interposer, which is the heart of 3D IC, and also the manufacturing process of the interposer. Lastly, the testing mechanism, application and challenges of 3D Integrated Circuits using TSVs will be discussed.	en_US
DC.subject	三維集成	zh_TW
DC.subject	三維集成封裝	zh_TW
DC.subject	三維集成電路	zh_TW
DC.subject	矽穿孔	zh_TW
DC.subject	中介層	zh_TW
DC.subject	3D integration	en_US
DC.subject	3D IC packing	en_US
DC.subject	3D IC	en_US
DC.subject	Through Silicon Via	en_US
DC.subject	TSV	en_US
DC.subject	Interposer	en_US
DC.title	三維集成電路的發展與挑戰	zh_TW
dc.language.iso	zh-TW	zh-TW
DC.title	The Development and Challenges of 3D IC	en_US
DC.type	博碩士論文	zh_TW
DC.type	thesis	en_US
DC.publisher	National Central University	en_US