| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 林郁芸 | zh_TW |
| DC.creator | Yu-Yun Lin | en_US |
| dc.date.accessioned | 2017-5-3T07:39:07Z | |
| dc.date.available | 2017-5-3T07:39:07Z | |
| dc.date.issued | 2017 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:444/thesis/view_etd.asp?URN=103521010 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 現今新興的超低功率消耗的應用，越來越受到大家的關注與重視。為了達到超低功率消耗的需求，以延長產品使用時間，次臨界區(Sub-threshold)電路設計提供了一種解決方法，藉由操作在極低電壓 (Vdd| zh_TW | |
| dc.description.abstract | Power has become the primary design constraint for chip designers today. To reduce power and increase service time, low-voltage low-power design becomes more and more important. One of the possible ways to achieve this goal is sub-threshold circuit design. By operating transistors at the region that Vdd is less than the transistor threshold voltage (Vdd| en_US | |
| DC.subject | 次臨界區 | zh_TW |
| DC.subject | 兩級式運算放大器 | zh_TW |
| DC.subject | 類比設計自動化 | zh_TW |
| DC.subject | Sub-threshold | en_US |
| DC.subject | Two-stage-OPA | en_US |
| DC.subject | Design Automation | en_US |
| DC.title | 次臨界區運算放大器電路之自動化設計 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Design Automation for Sub-Threshold Operational Amplifier Circuits | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |