| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 吳治成 | zh_TW |
| DC.creator | Zhi-Cheng Wu | en_US |
| dc.date.accessioned | 2016-8-26T07:39:07Z | |
| dc.date.available | 2016-8-26T07:39:07Z | |
| dc.date.issued | 2016 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:444/thesis/view_etd.asp?URN=103521108 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 金氧半場效電晶體(MOSFET)是以漂移-擴散的機制來傳導電流，受限於此機制，其開關時閘極需要至少60 mV來改變十倍的通道電流，也就是其次臨限擺幅(Subthreshold Swing)最理想狀況下僅能降至60 mV/decade。在考慮低功率損耗時，具有陡峭開關特性的穿隧式場效電晶體(TFETs)被認為有應用在新世代CMOS元件的潛力。目前，國內外已經有許多的矽/鍺材料穿隧式場效電晶體研究成果，優點是容易與傳統矽材料/元件整合且製程成熟度高，但缺點是材料能隙大且能帶組合受限，導致穿隧電流偏低或漏電流太大，因此以能隙較小的三五族材料搭配異質結構能帶工程，或可解決上述問題，成為未來穿隧式場效電晶體的選擇。本論文即以三五族異質接面穿隧場效電晶體為研究對象，利用模擬方式研究如何設計常關型、高電流、低次臨限擺幅的穿隧場效電晶體結構。研究內容包括建立三五族穿隧場效電晶體物理模型，以具第二型異質接面的銻砷化鎵/砷化銦鎵(GaAsSb/InGaAs)結構為主，模擬元件磊晶結構、閘極氧化層位置、材料缺陷和摻雜濃度等參數對元件直流特性之影響。模擬結果顯示，吾人可改變銻砷化鎵/砷化銦鎵結構之成分組合而降低穿隧的等效位能障，以有效提高導通電流，但也同時會提高關閉時之漏電流，此一致命的缺點將使穿隧式電晶體無法運用在節能電路之中。因此，吾人以能帶工程的方式，將GaAs0.51Sb0.49/In0.53Ga0.47As源極-通道接面之間加入一層砷化銦(InAs)量子井，將源極-通道接面的等效位障由0.5 eV降至0.1 eV，藉此將導通電流提高至89 μA/μm，同時將漏電流維持在5×10-8 μA/μm，此接面能帶的調整對於元件特性有相當顯著地提升。為了持續優化直流特性，吾人提出以具組成梯度(Graded)的砷化銦鎵量子井來取代上述之砷化銦量子井，使元件同時具有高導通電流與低漏電流的特性，並且具有高於50 mV的臨限電壓以降低閘極雜訊之影響，完成高導通電流常關型穿隧式場效電晶體之設計。 | zh_TW |
| dc.description.abstract | Since the channel current of MOSFETs is governed by the drift-diffusion mechanism, their subthreshold swing is limited to 60 mV/decade or higher at room temperature. Whereas, tunnel field-effect transistors (TFETs), whose current conduction is based on quantum mechanical band-to-band tunneling mechanism that gives a sub-60 mV/decade subthreshold slope, have been considered a promising energy-efficient device for low voltage and low power circuits. Since the inception of this proposal, TFETs based on Si/Ge material system have been demonstrated by a few groups. However, the devices are limited by either a low on-current or a high off-current due to the unfavored bandgap and band alignment of Si/Ge. Attention is then switched to narrow bandgap III-V compounds as the aforementioned issues could be solved by band gap engineering. This study is focused on III-V TFETs, aiming at the design and analysis of a normally-off TFET with high-on current. It covers the setup of a physical model in the TCAD tool, the effects of band alignments, gate position, and doping concentration on the electrical properties of the type-II band lineup GaAsxSb1-x/InyGa1-yAs heterojunction TFETs. Our simulation indicate that although GaAsxSb1-x/InyGa1-yAs TFETs could be designed to have a small Ebeff at the hetero-interface for high-on current, their high off-state current manifest themselves unacceptable for practical use. To solve this issue, a GaAs0.51Sb0.49/InAs/In0.53Ga0.47As TFET with an InAs quantum well (QW) is proposed to reduce the Ebeff from 0.5 eV to 0.1 eV at the source/channel interface, leading to an on-state current increasing from 27 A/m to 89 A/m at VGS=VDS=0.5 V, while the IOFF still maintains on the order of 10-7 μA/μm at VGS=0 V, simultaneously. To improve the device performance further and increase noise immunity at the gate, a graded InGaAs QW is designed to replace the InAs QW in the GaAs0.51Sb0.49/In0.53Ga0.47As TFET above. On this design, a normally-off TFET with high on-state current and threshold voltage greater than 50 mV has been achieved. | en_US |
| DC.subject | 銻砷化鎵/砷化銦鎵 | zh_TW |
| DC.subject | 穿隧式場效電晶體 | zh_TW |
| DC.subject | GaAsSb/InGaAs | en_US |
| DC.subject | Tunneling Field-Effect Transistors | en_US |
| DC.title | 具高導通電流常關型銻砷化鎵/砷化銦鎵異質接面穿隧式場效電晶體之研究 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Bandgap Engineering for Normally-off GaAsSb/InGaAs Hetero-junction Tunneling Field-Effect Transistors with High On-state Current | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |