| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 沈沛謙 | zh_TW |
| DC.creator | Pei-Chien Shen | en_US |
| dc.date.accessioned | 2018-8-6T07:39:07Z | |
| dc.date.available | 2018-8-6T07:39:07Z | |
| dc.date.issued | 2018 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:444/thesis/view_etd.asp?URN=105521018 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 本論文研究內容主要探討閘極掘入式氮化鋁鎵/氮化鎵金絕半電容與閘極掘入式氮化鋁鎵/氮化鎵金絕半場效電晶體，一般常見的製程流程是先蒸鍍歐姆金屬後進行歐姆金屬的快速熱退火，熱退火完才進行閘極掘入。本論文所使用之製程流程是蒸鍍完歐姆金屬後先進行閘極掘入，待閘極掘入完畢後再與歐姆金屬一起進行快速熱退火，達到歐姆接觸跟閘極蝕刻後界面改善之目的。
在高蝕刻率閘極掘入式氮化鋁鎵/氮化鎵金絕半電容之特性方面，閘極掘入後經過快速熱退火處理有效改善電容的調變率、遲滯現象及頻散現象。而在閘極介電層與半導體的界面，在閘極掘入後經過快速熱退火處理也有獲得改善，且發現使用低蝕刻率之閘極掘入所製作而成的電容有最佳的界面品質。
在高蝕刻率閘極掘入式氮化鋁鎵/氮化鎵金絕半場效電晶體方面，閘極掘入後經過快速熱退火，使得元件從增強型元件轉變成空乏型元件。但在最大增益轉導值、最大汲極電流值、最小次臨界擺幅、導通電阻、元件關閉時的漏電流方面，皆是閘極掘入後經過快速熱退火之特性較佳，且由遲滯效應去估算介面缺陷密度，跟電容之電導法萃取有相似的趨勢。最後使用低蝕刻率之閘極掘入所製作而成的金絕半場效電晶體擁有最佳的元件特性 (Vth = 2.12 V、ID, max = 233.24 mA/mm、(I_on/I_off ) = 1.73 107，μmax = 143.14 cm2/Vs)。 | zh_TW |
| dc.description.abstract | In this study, a new process flow was proposed, which is ohmic contact annealing and post etching annealing at the same time to improve the surface states after gate recess and form good ohmic contact. The enhancement mode (E-mode) GaN MIS-FETs and MIS-capacitor with recessed gate were fabricated and investigated. And the difference in device DC performances when device with proposed annealing and device with traditional ohmic annealing are compared.
In recessed-gate MIS-capacitor with high etching rate, device with proposed annealing (annealing after gate recess) shows better capacitance modulation, capacitance dispersion and lower hysteresis than the device with traditional ohmic annealing (without annealing after gate recess). The interface state density between the gate dielectric layer and the semiconductor has been effectively improved in devices with proposed annealing. In addition, it has been found that using a low etching rate to produce the recessed-gate MIS-capacitor could result in the best interface quality.
In recessed-gate MIS-FET with high etching rate for gate recess, device with proposed annealing turns into depletion-mode operation from enhancement-mode operation, but gm, max, ID, max, S.S.min, Ron, leakage current at off state are better than device with traditional annealing. The hysteresis effect in device I-V characteristics is used to estimate the interface state density, which is similar to the conductance extraction result in C-V measurements. Finally, MIS-FET with low etching rate for gate recess process emonstrates the best device characteristics, and is our laboratory′s first GaN enhancement mode device. | en_US |
| DC.subject | 氮化鎵 | zh_TW |
| DC.subject | 閘極掘入 | zh_TW |
| DC.subject | 閘極蝕刻後熱退火 | zh_TW |
| DC.subject | GaN | en_US |
| DC.subject | gate recess | en_US |
| DC.subject | post etching annealing | en_US |
| DC.title | 閘極掘入式氮化鋁鎵/氮化鎵增強型場效電晶體之閘極蝕刻後熱退火研究 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | The investigation of Enhancement-mode AlGaN/GaN Recessed Gate Field-Effect Transistors with Post Etching Rapid Thermal Annealing Process | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |