| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 郭語璇 | zh_TW |
| DC.creator | Yu-Hsuan Kuo | en_US |
| dc.date.accessioned | 2018-7-27T07:39:07Z | |
| dc.date.available | 2018-7-27T07:39:07Z | |
| dc.date.issued | 2018 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:444/thesis/view_etd.asp?URN=105521029 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 近年來隨著製程技術的進步，積體電路(IC)設計進入了深次微米(deep-submicron)技術時代，當元件尺寸(device size)越來越小，製程變異(process variation)和電路老化(circuit aging)現象對於電路效能的影響也越來越顯著，甚至威脅到電路的可靠度，對於敏感的類比電路來說更為嚴重。因此，若是可以在設計初期，就將可能造成參數變異的現象考慮進來，事先預防對電路效能的不良影響，就可以大幅降低重新設計的成本，提高電路的良率。為了評估製程變異、元件老化等參數變化所造成的效能飄移，最常見的方法是做蒙地卡羅模擬(Monte Carlo Simulation)，然而，電路老化效應是一個漸進式的過程，若要將此一同加進來做分析，相當於每隔一段時間就要做一次蒙地卡羅分析，雖然可以達到較高的精準度，但模擬所需的時間和代價卻非常高昂。
為了加速老化分析的效率，先前的研究[7]提出了基於戴爾他模型的漸進式模擬技術，還提出了一種動態的採樣技術，進一步減少模擬的次數。此外，在文獻中，行為模型除了協助設計者進行功能驗證外，對於其他類型的驗證，也都有很好的加速效果，被廣泛地用於加速電路的模擬。因此，本論文將老化現象加入行為模型中，加速老化分析的過程，再結合漸進式模擬技術，將它從電晶體層級提升到行為層級中，來提升壽命良率分析的效率。由實驗結果觀察可知，本論文所提出的方法確實有效提升了電路壽命良率分析的效率，也能同時保有其原本的精準度，是ㄧ個兼顧效能與準確度的好方法。 | zh_TW |
| dc.description.abstract | With the shrinking device size in deep-submicron era, the parameter shift due to process variation and aging effects has an increasing impact on the circuit yield and reliability, especially for sensitive analog circuits. If we can consider the impact of device parameter variation for the circuit performance at early design stages, it can help to significantly reduce the re-design cost and increase circuit yield. To assess the effective drift by the process variation, Monte Carlo (MC) analysis is often used. Since aging process is often a gradual change, we have to analyze the circuits repeatedly after a period of time. For modern large circuits, performing MC simulation repeatedly during aging analysis is almost infeasible due to the high complexity.
In order to improve the efficiency of aging analysis while keeping high accuracy, an incremental simulation technique is proposed in [7] based on delta circuit models. A dynamic aging sampling technique is also proposed to further reduce the number of simulations. In the literature, analog behavioral models are widely used to speed up circuit simulation. In this thesis, we try to combine delta models and behavioral models in aging analysis and develop proper behavioral models to simulate the degraded performance distribution instead of transistor-level simulation. After promoted to behavioral level, it is possible to have more improvements on the efficiency of lifetime yield analysis. As demonstrated in the experimental results, the proposed approach is indeed an effective way to improve the efficiency of lifetime yield analysis while keeping estimation accuracy. | en_US |
| DC.subject | 類比電路分析 | zh_TW |
| DC.subject | 行為模型 | zh_TW |
| DC.subject | 電路老化 | zh_TW |
| DC.subject | 可靠度改善 | zh_TW |
| DC.subject | Analog Circuit Analysis | en_US |
| DC.subject | Behavioral Model | en_US |
| DC.subject | Circuit Aging | en_US |
| DC.subject | Reliability Improvement | en_US |
| DC.title | 以類比電路行為模型提升電路壽命分析的效率 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Efficient Lifetime Yield Analysis with Analog Behavioral Models | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |