| dc.description.abstract | In recent years, according to the rapid development of the process and computers, the series data transmission is widely used for the bus instead of the parallel transmission and the data rate increases progressively, such as PCI-Express, SATA, USB and SONET in the fiber network. The data rate has even risen up to ten billion bits per second in the latest generation specifications. Therefore, the circuit design complexity is greatly increased.
In this paper, a full-rate data and clock recovery circuit for symmetric edge detection technique of PAM-4 is implemented with reference to USB 3.1 Gen2, and a new phase detector for PAM-4 is proposed. A large number of circuits are used to detect the PAM-4 signal, which leads to increase in overall power consumption. In addition, the edge of the PAM-4 is differentiated, so that the undesired edges are ignored, so that the recovered clock jitter is reduced. Moreover, a new transition detector is proposed, which uses only a single logic gate to achieve the effect of the transition detection, and combines it with the traditional bang-bang phase detector to reduce the overall circuit area and reduce the power consumption. This paper uses TSMC 40 nm (TN40G) 1P10M CMOS process, the operating voltage is 0.9 V, the input data is 10 Gbps PAM-4, the recovered clock rate is 5 GHz, the peak value of the recovered clock is 27.5 pspp, and the root mean square value is 4.31 psrms. The power consumption is 24.7 mW, the chip area is 1.11 mm2, and the core area is 0.094 mm2.
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