| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 廖偉筑 | zh_TW |
| DC.creator | Wei-Chu Liao | en_US |
| dc.date.accessioned | 2020-6-18T07:39:07Z | |
| dc.date.available | 2020-6-18T07:39:07Z | |
| dc.date.issued | 2020 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:444/thesis/view_etd.asp?URN=106521026 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 隨著積體電路技術的快速發展，現今矽晶圓廠的生產技術已發展至5奈米節點，電晶體性能逐漸接近物理極限，需要尋找新架構且容忍度較大之通道材料來突破。根據產業技術發展的情形，具有高電子遷移率的Ⅲ-Ⅴ族砷化銦鎵與具有高電洞遷移率的鍺，被認為是製作N型與P型場效電晶體具有潛力的材料。因此，如何實現異質整合之鍺與砷化銦鎵互補式金氧半電晶體是未來量產化的關鍵技術之一。本研究率先開發於矽基板上製備鍺模板，接著以有機金屬化學蒸氣沉積法（MOCVD）選擇性成長砷化鋁銦/砷化銦鎵於其上，並研製鰭式場效電晶體（FinFET）。
本研究比較乾式與濕式蝕刻方式將鍺溝槽底部形貌之影響，並觀察其對後續選擇性磊晶砷化鋁銦所產生之缺陷多寡及對元件特性之影響。此二法所製作之砷化銦鎵鰭式場效電晶體在通道寬度100奈米與閘極長度為60奈米下之最大電流密度分別為77.8 μA/μm及74 μA/μm，次臨界擺幅（S.S.）分別為468 mV/dec.與810 mV/dec.，二者之閘極漏電密度則皆低於5×10-6 μA/μm。此研究所製作之鍺鰭式場效電晶體於通道寬度40奈米閘極長度為60奈米之最大電流密度為35 μA/μm，次臨界擺幅（S.S.）為2217 mV/dec.，而閘極漏電密度為2.47×10-5 μA/μm。此研究已將三五族與鍺鰭式場效電晶體整合於矽基板上，未來在優化選擇性成長技術與閘極製程技術後，應可降低次臨界擺幅、提升汲極電流密度、降低閘極漏電流密度。 | zh_TW |
| dc.description.abstract | While Si complementary metal-oxide-semiconductor (CMOS) manufacturing technology comes to 5 nm technology nodes, current transistor technology is also approaching its physical limit. The quests for energy efficient transistors and high mobility channel materials have provoked tremendous research efforts worldwide in recent years. Among the options that are closer to reality, InGaAs and Ge, which has high electron mobility and high hole mobility, respectively, are of great interest for n-channel and p-channel materials. Heterogeneous integration of these two materials on Si substrate is therefore a key technology to develop for future mass production. This study concerns the fabrication of InGaAs fin field-effect transistors（FinFETs）using selective area growth (SAG) in Ge trenches on Si substrates by MOCVD.
In this study, the Ge trenches were prepared by dry etching and wet etching methods to investigate how the resultant trench morphology affects the growth of InAlAs/InGaAs fins and the device characteristics. The maximum current density of the InGaAs FinFETs fabricated by these two methods devices is 77.8 μA/μm and 74 μA/μm with a sub-threshold swing (S.S.) of 468 mV/dec and 810 mV/dec, respectively, for the devices with a channel width of 100 nm and a gate length of 60 nm. The gate leakage density of both devices is lower than 5×10-6 μA/μm. The maximum current density of the Ge FinFETs with a channel width of 40 nm and a gate length of 60 nm is 35 μA/μm, and has a sub-threshold swing (S.S.) of 2217 mV/dec. The gate leakage density is 2.47×10-5 μA/μm.
This work demonstrates the integration of InGaAs and Ge FinFETs on a Ge/Si template. In-depth analysis indicates that further optimization on the selective area growth and gate-stack processes is required to achieve higher drain current density and lower sub-threshold swing. | en_US |
| DC.subject | 鰭式場效電晶體 | zh_TW |
| DC.subject | 砷化銦鎵 | zh_TW |
| DC.subject | 鍺 | zh_TW |
| DC.subject | Fin Field-Effect Transistors | en_US |
| DC.subject | InGaAs | en_US |
| DC.subject | Ge | en_US |
| DC.title | 矽基鍺模板上N通道砷化銦鎵及P通道鍺鰭式場效電晶體之研製 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Fabrication of n-channel InGaAs and p-channel Ge Fin Field-Effect Transistors on Ge/Si Templates | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |