| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 蘇正瑋 | zh_TW |
| DC.creator | Cheng-Wei Su | en_US |
| dc.date.accessioned | 2021-1-20T07:39:07Z | |
| dc.date.available | 2021-1-20T07:39:07Z | |
| dc.date.issued | 2021 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:444/thesis/view_etd.asp?URN=107521001 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 隨著製程技術的演進、EUV(Extreme ultraviolet lithography)的引進，使電晶體可以進一步微縮，並讓晶片上可以容納更多的電晶體，與此同時，內部繞線(Interconnect)的結構也勢必變小，因此增加了後段製程(BEOL)的金屬電阻值，這樣的情況會使電路的特性變差。因此，本論文利用積層型三維(Monolithic 3D)堆疊技術，設計三維的靜態隨機存取記憶體(Static Random Access Memory, SRAM)電路佈局來改善其特性。
本論文主要探討的電路是SRAM，利用TCAD的Mixed-Mode及內部導線模型(π-3 Model)來分析SRAM的電路特性。論文內容分為三個主題，第一部分會探討先進技術節點下內部導線的微縮對SRAM電路所產生的影響，研究結果顯示內部導線電阻值的增加會延長傳輸訊號的時間使SRAM電路特性有顯著的退化。第二部分，我們利用Transistor-Level積層型三維堆疊來設計SRAM，Transistor-Level積層型三維堆疊是將P型跟N型電晶體製作在不同的平面上，可以調整製作流程並獨立優化電晶體特性，不但能縮小SRAM的單元(cell)面積也能減少內部導線的繞線長度，使字元線及位元線的電阻電容值降低，考慮在一/二/三層的積層型三維SRAM的佈局下，分析SRAM cell的讀取存取時間(Read access time)、寫入時間(Time-to-write)、動態能量消耗及能量延遲積。
第三部分，我們探討未來具有潛力的通道材料—二維材料，分析不同閘極位置的二氧化鉬場效電晶體及積層型三維堆疊的6T SRAM佈局優化，再比較由背閘極式場效電晶體組成的積層型三維SRAM的特性，由分析結果可得知三層積層型三維SRAM與一層相比可以改善28.4%讀取存取時間、21.3%動態能量及43.6%能量延遲積，並增強寫入的穩定度。本篇論文提出的高能量效率背閘極式三層積層型三維SRAM，具有更好的潛力應用在邊緣運算裝置中。 | zh_TW |
| dc.description.abstract | With the evolution of process technology and the introduction of EUV, transistors can be scaled down and more transistors can be accommodated on the wafer. Continued scaling of the transistor and metal interconnection geometry is accompanied by the increased wire routing resistance which degrades the circuit performance. Therefore, the thesis uses monolithic 3D stacking technology to design a three-dimension SRAM circuit layout to improve SRAM characteristics.
The thesis mainly explores static random access memory, we analyze SRAM performance by using TCAD coupled with the interconnect π-3 model. In the first part, we discuss the impact of scaled interconnect metal on SRAM circuits in advanced technology nodes. The research results show that increased back-end of line metal resistance prolongs the signal transmission time and degrades SRAM performance significantly.
In the second part, we design SRAM with transistor-level monolithic 3D integration. In transistor-level M3D design, p-type and n-type transistors are fabricated on different layers. Thus, PMOS and NMOS devices can be optimized separately. It can reduce not only the SRAM cell area, but also interconnect lengths that makes wire routing resistance and capacitance low. And we analyze the cell area, read access time, time-to-write, and energy efficiency in 1-tier, 2-tier, and 3-tier monolithic 3D SRAM cell.
In the third part, we discuss potential channel materials—2D material and comprehensively analyze gate topology of MoS2 FETs, and the layout optimization of multi-tier 6T SRAM cells. Compared to the multi-tier back-gated(BG) SRAM cell designs, the monolithic 3-tier BG SRAM cell shows 28.4% read access time, 21.3% dynamic energy, and 43.6% energy-delay product improvements over 1-tier BG SRAM and enhance the write stability. The energy- and area-efficient 3-tier BG SRAM cell enables intelligent functionalities for the area and energy-constrained edge computing devices. | en_US |
| DC.subject | 積層型三維堆疊 | zh_TW |
| DC.subject | 二維材料 | zh_TW |
| DC.subject | 後段製程 | zh_TW |
| DC.subject | 靜態隨機存取記憶體 | zh_TW |
| DC.subject | 能量效率 | zh_TW |
| DC.subject | Monolithic 3D integration | en_US |
| DC.subject | 2D material | en_US |
| DC.subject | back-end-of-the-line (BEOL) | en_US |
| DC.subject | SRAM | en_US |
| DC.subject | energy efficiency | en_US |
| DC.title | 考慮後段製程連線及佈局優化之積層型三維靜態隨機存取記憶體 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Multi-tier Monolithic 3D SRAM Considering BEOL Interconnect and Layout Optimization | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |