| dc.description.abstract | With the successive development of Artificial Intelligence (AI) and Internet of Thing (IoT), the communication between memory and processing units becomes a serious challenge due to high power consumption and low data throughput. In general, the processing speed is faster than the read/write speed of the memory, which leads to the Von Neumann bottleneck. Moreover, with the recent discovery of ferroelectricity in HfO2, the novel ferroelectric FET (FeFET) based non-volatile memory is alleviated the Von Neumann bottleneck by computing inside the logic memory units and eliminating the energy-intensive and time-consuming data movement.
In the first part, TCAD simulations for FeFET are coupled with Preisach model, and then we analyze and simulate the characteristic of memory window. The two inputs used to perform the logic functionality of the FeFET can be obtained through ferroelectric polarization state and gate voltage, whereas the potential at source and back-gate are utilized to shift the transfer characteristics towards higher (or lower) gate bias to obtain all the logic states corresponding to input combinations. The circuit used to perform NOR or NAND logic operation consists of single FeFET with a pull up resistor in series. The functionality of pull-up resistor is to transform the current state to the output voltage. It is shown that NOR and NAND logic functionality can be realized with 1T FeFET, and then we can analyze the design space comprehensively and quantitatively by applying source and back-gate voltage. We also analyze the impact of ferroelectric parameter variations on the design space, and we can know the back-gate voltage providing wider design space in the nominal and ferroelectric variations. The comparisions of propagation delay, power delay product (PDP), and energy delay product (EDP) of FeFET NAND logic gate with optimal source and back-gate voltage have been analyzed. The optimal back-gate voltage shows improvement in delay time, PDP, and EDP with optimal source voltage.
In the second part, we use split-gate FeFET to achieve NOR, NAND, and XNOR logic functionality. In contrast to single gate FeFET, split-gate FeFET uses two front gates to achieve the logic operation. One gate is fixed at constant voltage to shift the Ids-Vgs curve towards lower (or higher) gate bias, and another gate is provided with ferroelectric polarization state and gate voltage as the inputs. This method achieves NOR and NAND logic function by modulating one gate, and the design space of the gate voltage in split-gate FeFET is analyzed comprehensively and quantitatively. To further demonstrate the advantages of using split-gate device structure, the thesis explores the AOI (AND-OR-INVERTER) circuit. The AOI circuit uses the NAND, NOT, and NOR logic functions. Results highlight that split-gate FeFET can replace conventional NAND logic function in the AOI logic circuit, and thus it reduces the number of transistors in the conventional AOI circuit. Moreover, the results obtained from AOI circuit designed with the split-gate are comparable with conventional AOI circuit. Furthermore, the thesis explores the XNOR logic operation using split-gate and conventional FeFET. Results show that split-gate FeFET lowers the writing voltage in XNOR logic function.
Keywords: Ferroelectric, Von Neumann bottleneck, ferroelectric FET, split-gate FeFET, non-volatile memory, memory window, logic in memory, variability, design space | en_US |