| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 李承哲 | zh_TW |
| DC.creator | Cheng-Jhe Lee | en_US |
| dc.date.accessioned | 2021-9-30T07:39:07Z | |
| dc.date.available | 2021-9-30T07:39:07Z | |
| dc.date.issued | 2021 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:444/thesis/view_etd.asp?URN=107521033 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 近年來，MIMO (Multi-Input Multi-Output 多輸入多輸出)系統在無線通訊的發展日新月異。其不只能夠大量增加系統的吞吐量，更能夠藉由使用多天線來提升效能。首先本文深入探討不同的奇異值分解(Singular Value Decomposition, SVD)硬體演算法，像是2-sided Jacobi、Golub-Kahan等，並分別對其優點與缺點做出分析。接下來，本文講述使用的Givens Rotation SVD (GR-SVD)演算法，並講述選用此演算法的好處。本文以室內多輸入多輸出系統環境切入，並分析其環境跟一般無線通訊環境的不同，並指出室內多輸入多輸出系統相對於一般無線通訊系統的優缺點。本文使用分區對角化預補償作為硬體實現的目標，模擬分析分區對角化預補償的效果，並且據此設計能夠搭配2x2 4用戶、4x4 2用戶、8x8 1用戶之高速奇異值分解，使得用戶的靈活度大幅度提高，對應未來天線數的增加有大幅助益。本文介紹了硬體設計的考量跟電路的運作模式，詳細敘述了如何克服硬體電路設計中的困難跟挑戰。經由NC-Verilog來驗證電路邏輯，最後我們將電路輸出結果跟Matlab來做交叉比對，並使用TSMC-40nm製程來實現硬體電路。詳述了Cell-Based的設計流程，展示出如何使用Design Compiler跟 IC Compiler，我們從設計結果可以得知面積跟功耗都有不小的改善。最後再用本文設計結果來和其他論文及參考資料做比較，並得出本文設計結果的優點與缺點。 | zh_TW |
| dc.description.abstract | In recent years, MIMO (Multi-Input Multi Output) has become a significant system. MIMO techniques bring many benefits to communication system, such as higher throughput and reliability. However, more different configurations of antennas between transceivers and receivers, there are a few issues to be solved. In this thesis, Indoor VLC MIMO system is investigated. At first, difference between normal MIMO wireless system and Indoor VLC MIMO system is discussed. Then, SVD (Singular Value Decomposition) technique is presented, which is a common used technique for precoding. In order to increase the flexibility, the block diagonalization precoding is employed to support Multi-user. This thesis proposes a reconfigurable architecture which can compute SVD for 2x2 for four users, 4x4 for two users, 8x8 for one user. This design archives low area and low power. The proposed architecture is implemented with TSMC-40nm technology. Finally, we compare with the literature, we can find the propose architecture brings high power efficiency. | en_US |
| DC.subject | 奇異值分解 | zh_TW |
| DC.subject | 可見光通訊 | zh_TW |
| DC.subject | 多輸入多輸出 | zh_TW |
| DC.subject | 可重構 | zh_TW |
| DC.subject | 分區對角化預補償 | zh_TW |
| DC.subject | Singular Value Decomposition | en_US |
| DC.subject | Visible Light Communication | en_US |
| DC.subject | Multi-Input Multi-Output | en_US |
| DC.subject | Reconfigurable | en_US |
| DC.subject | Block Diagonalization Precoding | en_US |
| DC.title | 使用分區對角化預補償於室內可見光多模式多輸入多輸出的可重構之高速奇異值分解處理器 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Reconfigurable Multi-mode SVD Processor for Indoor VLC Multi-user MIMO System with Block Diagonalization Precoding | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |