| dc.description.abstract | With the advancement of technology, the data transmission rate has been continuously improved. High-speed serial link technology has gradually replaced the traditional parallel transmission, such as HDMI, Displayport, USB, SATA, PCI-Express. However, the attenuation of the data through the transmission channel is more serious, because the channel bandwidth does not increase accordingly. Therefore, the equalizer is widely used at receiver to compensate the data to increase the signal integrity.
This thesis proposed a feed-forward equalizer at the receiver, the inter-symbol-interference (ISI) can be eliminated by using the analog delay circuit to delay the input signal, and multiplies a weight coefficient. Compared with the traditional architecture, it does not need to use the clock for sampling and buffer circuits, so the power consumption can be reduced while maintaining the data amplitude. In addition, the continuous time linear equalizer (CTLE)、 feed-forward equalizer (FFE) and 1-tap discrete-time decision feedback equalizer (1-tap DT-DFE) are be used in data compensation. As the result, the proposed adaptive receiver system not only reduce the complexity of hardware and power consumption, but also can be widely used for 7-33 dB channel loss application.
This chip is fabricated by TSMC 40 nm (TN40G) 1P10M CMOS process. In simulation result, the input is 10 Gb/s PRBS7 NRZ data, and the 10 GHz full rate clock be adopted. In 7-dB channel loss, 22 % improvement in eye height after compensation. In 33-dB channel loss, 47 % improvement in eye height after compensation. The overall power consumption of whole receiver consumes 18.88 mW at 0.9 V supply voltage. The chip area with 40 nm which is scaling down by 45 nm is 1.060 mm2 and core area is 0.026 mm2. | en_US |