| DC 欄位 |
值 |
語言 |
| DC.contributor | 機械工程學系 | zh_TW |
| DC.creator | 王又霆 | zh_TW |
| DC.creator | Yu-Ting Wang | en_US |
| dc.date.accessioned | 2021-10-22T07:39:07Z | |
| dc.date.available | 2021-10-22T07:39:07Z | |
| dc.date.issued | 2021 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:444/thesis/view_etd.asp?URN=108327002 | |
| dc.contributor.department | 機械工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 本論文提出為了善用5G網路速度而自行開發之高速擷取系統，使用Digilent公司之開發板上類比數位訊號轉換器(Analog-to-digital converter, ADC)與現場可程式化邏輯閘陣列（Field Programmable Gate Array, FPGA）作為核心處理器，撰寫內部VHDL程式後進行燒錄，最後使用C語言進行開發應用程式，並搭配第五代行動通訊技術（5th generation mobile networks, 5G）內網進行資料之傳輸，從感測器接受資訊後ADC進行轉換並由FPGA進行暫存與排序，最後連接內網路由器進行聯網，傳輸資料至終端伺服器。 | zh_TW |
| dc.description.abstract | This paper proposes a self-developed high-speed acquisition system to make good use of the 5G network speed, using Digilent’s development board analog-to-digital converter (ADC) and field-programmable logic gate array ( Field Programmable Gate Array (FPGA) is used as the core processor. After writing the internal VHDL program, it is burned. Finally, the C language is used to develop the application program, and it is used with the fifth-generation mobile networks (5th generation mobile networks, 5G) intranet for data. For transmission, after receiving the information from the sensor, the ADC performs the conversion, and the FPGA performs temporary storage and sorting. Finally, it is connected to the intranet router for networking, and the data is transmitted to the terminal server. | en_US |
| DC.subject | 高速擷取系統 | zh_TW |
| DC.subject | FPGA | en_US |
| DC.subject | ADC | en_US |
| DC.subject | 5G | en_US |
| DC.title | 以ADC與FPGA實現5G通訊高速訊號擷取系統之開發 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |