| dc.description.abstract | This thesis presents three chips for 5th generation communication system applications. Two of them were designed in WINTM 0.25-μm GaN/SiC, the first one is a Doherty power amplifier (DPA) for n77-band apllications, the second one is a continuous class-F power amplifier for C-band applications. The third PA was a stacked power amplifier fabricated in tsmcTM 0.18-μm CMOS for C-band applications. All three chips have been implemented and measured, including scattering parameters, large signal, and 5G NR FR1 modulation signal measurements. The chips were using the optimized bias conditions and pre-distortion methods to make each circuit have the best circuit performances.
Chapter 2 presents an n77-band GaN DPA, by utilizing transformers to its output matching network, it improves the bandwidth of the DPA. To improve the power added efficiency (PAE) at the power back-off (OPBO) operation condition, an unequal power splliter was adapted at the input of the PA. The measurements achieve a peak power gain of 9.09 dB, a bandwidth of 2.8 to 3.6 GHz, a fractional bandwidth (FBW) is 25%. Due to the limit on large signal measuments, the DPA was unable to achive its saturation output power. According to the measured data, the saturation power is 34.5 to 35.5 dBm and the maximun PAE is 30 to 40.2%, the PAE at 6-dB OPBO is 20.7 to 22.8% in the operation band. The chip area is 9 mm2 which core area is 5.63 mm2. The modulaion measurement result shows that the best EVM performance at 22-dBm input power by using DPD and CFR techniques.
Chapter 3 presents a C-band class-F continuous mode GaN PA. By analyzing the large signal transconductance (Gm), the appropriate gate bias was selected to improve AM-AM linearity. To achieve class-F continuous mode operation, three resonators were applied at the output matching network. On the other hand, a band pass filter with two resonators were used at the input matching network for wide band operation. The measurements achieve a peak power gain of 15.02 dB, a bandwidth of 4.0 to 5.4 GHz, and a fractional bandwidth (FBW) of 29.8%. The measured large signal performances show that a saturation power of 36.4 to 37.8 dBm, a maximun PAE of 21.4 to 28%, an output 1-dB compression power of 30.4 to 35 dBm, and a PAE of 17 to 28 %. The chip area is 5 mm2. The modulaion measurement shows that the PA achieves the best EVM at 18-dBm input power by using DPD and CFR techniques.
Chapter 4 presents a C-band CMOS stacked PA which uses a set of stacked driver cell to drive two differential stacked power cell. All of the matching network were designed with transformers to achieve broadband frequency response. The measurements achieve a peak power gain of 17.07 dB, a bandwidth of 3.2 to 5.4 GHz, a fractional bandwidth (FBW) of 51%. The measured large signal performances show that a saturation power of 23.04 to 24.73 dBm, a maximun PAE of 8 to 11.42%, an output 1-dB compression power of 20.4 to 22 dBm. The chip area is 3.685 mm2. Modulaion measurement shows that the PA presents the best EVM at 7-dBm input power by using DPD technique.
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