| dc.description.abstract | This paper mainly discusses the research on the injection-locked frequency divider and the four-phase phase-locked loop. In today′s millimeter-wave transceiver systems and radars, a stable oscillator source is required, and the local oscillator source is usually a Phase-locked loop. In addition, the injection-locked frequency dividers (ILFD) are also employed in the millimeter-wave PLL due to their high speed and low DC power consumption, and the ILFD can be adopted as the first-stage frequency divider in the PLL.
The sond chapter introduces the K-band Quadrature voltage-controlled oscillator applied to the phase-locked loop. This design uses the TSMC 0.18 μm CMOS process to complete the circuit design of this chapter. This chapter first introduces the theory of transformer-feedback and transformer-coupled, and then simulate the effects of different coupling coefficients and turns ratio on phase noise and output power for the two architectures. In addition, this chapter discusses several coupling methods, analyzes their coupling strength, and explains their advantages and disadvantages. Among them, self-injection coupling is selected to achieve a four-phase VCO. This circuit design successfully realized the K-band output signal. Two circuits, transformer feedback, and transformer feedback and coupling were used to design and compare performance. The frequency of the transformer-feedback is 22.94 GHz when the control voltage is 0 V. The output power is 22.94 GHz. When the control voltage is 1.8 V, the frequency is 24.5 GHz, the output power is -15.6 dBm, and the frequency adjustable range is 1.5 GHz. The best value for phase noise is -102 dBc at 1.5 V control voltage. The maximum phase error and amplitude error are 5.5 degrees and 1.8 dB, and the output power of transformer feedback and coupling is -15.2 dBm when the control voltage is 0 V and the frequency is 21.61 GHz; when the control voltage is 1.8 V, the output power is - 22.71 GHz. 15.9 dBm, frequency adjustable to 1.1 GHz. The best value for phase noise is -94.6 dBc at the control voltage of 1.3 V. Phase error and amplitude difference up to 8.2 degrees and 2.5 dB
In Chapter 3, a current-reused technique is employed in a V-band ILFD. The circuit design of the presented ILFD is first presented with some theoretical calculations and simulations. Furthermore, a double-injection technique is also employed in the ILFD circuit design to enhance the locking range, and the ILFD is realized using a TSMC 90-nm CMOS VI process. As compared with prior art, the proposed ILFD features wide locking range and low DC power. With an input power of 0 dBm, the measured locking range is 59.3 to 65.7 GHz, locking range is 6.4 GHz, which corresponds to a proportional bandwidth of 7 %, and the DC consumption of the circuit is 14.3 mW. Compared to analog, the injected signal power is 0 dBm, the bandwidth is 55.8 to 64.2 GHz, and the lock range is 8.4 GHz, which corresponds to a proportional bandwidth of 14%. Simulate and measure the center frequency offset 2.5 GHz and lock the bandwidth by 2 GHz. How to debug will be explained in this chapter.
In Chapter 4,K-band Quadrature phase-locked loop. The PLL is using TSMC 0.18 μm CMOS process design and implementation. The building blocks of the PLL include a QVCO, a phase-frequency detector, a charge pump, a loop filter, two-stage ILFD and two-stage common-mode logic dividers and three-stage true single phase clocking dividers. In the VCO, the tunning range is increased by 2 GHz, and the gain of the oscillator is increased by 1.8 GHz/V, which causes the phenomenon of loop oscillation. How to debug will be explained in this chapter. The locking range from 22.02 GHz to 23.49 GHz, measurement locking range from 22.189 GHz to 24.02 GHz, phase noise -90 dBc/Hz at 1 MHz frequency offset, total DC power consumption 90 mW | en_US |