| dc.description.abstract | In recent years, with the rapid development of the semiconductor industry, products require higher data transmission bandwidth, and high-speed serial transmission technology has become the mainstream for data transmission. In serial transmission systems, the RX needs to use clock and data recovery circuits (CDR) to readjust the input data clock to ensure accurate data recovery. However, various noise and signal attenuation may exist in the system, leading to an increase in error rates. Therefore, improving jitter tolerance (JTOL) and reducing Bit-Error-Rate (BER) have become design goals in clock and data recovery circuits.
This paper presents the implementation of a 5 Gbps phase-interpolator based clock and data recovery circuit with an adaptive loop gain controller (ALGC) based on the USB 3.2 Gen 1 specification.The adaptive loop gain controller detects the jitter frequency information of the input data, switches the loop gain of the data recovery loop, and optimizes JTOL under different jitter frequencies. This enhances the overall circuit′s jitter tolerance and reduces error rates. The adaptive loop gain improves low-frequency jitter tolerance by 132% and high-frequency jitter tolerance by 17%. The circuit is implemented using the TSMC 90 nm (TN90GUTM) 1P9M CMOS process, operates at 1 V, with a chip area of 1.49 mm², a core circuit area of 0.066 mm². At a data rate of 5 Gbps, the peak-to-peak jitter of the recovered clock is 14.7 pspp, the root mean square jitter is 3.46 psrms, and the power consumption is 31.04 mW. | en_US |