| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 周士淳 | zh_TW |
| DC.creator | Shih-Chun Chou | en_US |
| dc.date.accessioned | 2024-8-21T07:39:07Z | |
| dc.date.available | 2024-8-21T07:39:07Z | |
| dc.date.issued | 2024 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:444/thesis/view_etd.asp?URN=109521025 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 深度神經網路(DNN)已經被廣泛運用在人工智慧的應用當中。基於脈動陣列
的加速器經常用來加速DNN 的運算，加速器中包含許多相同的處理單元(PEs)。使用傳統的掃描鏈與自動測試圖樣產生(ATPG)技術是非常花費時間且不符合成本效益的。在這篇論文中，我們提出對角流水線掃描(DiPS)測試技術應用於脈動陣列加速器。DiPS 測試技術針對單一個PE 產生測試圖樣並且使用對角流水線的方式運用在整個陣列的處理單元上。DiPS 測試技術有著低測試複雜度和良好延展性的特色。DiPS 針對乘累加電路可覆蓋100%的延遲錯誤。針對n×m 的陣列測試的時間複雜度為(P×(S+1)+S+m+n-1)×2，其中P 為測試圖樣的數目，S 為單一PE 掃描鏈的長度。與先前的論文比較，被陣列大小影響的時間複雜度可以從(m+n)×P 下降到(m+n-1)×2。此外，我們基於DiPS 方法提出了錯誤定位方法。藉由比
對同一對角線上相鄰PE 的掃描鏈輸出來定位出錯誤PE 的位置。這個方法還能夠將陣列的掃描鏈輸出數目從m×n/2 減少到(m+n-2)/2。最後，我們設計了自我測試和自我修復(BISR)電路應用於一備用列的脈動陣列。針對32×32 的陣列假設PE 的錯誤率為0.1%到1%之間，BISR 技術可以提升8.79%到62.09 的良率。 | zh_TW |
| dc.description.abstract | Deep neural networks (DNN) are widely used in the artificial intelligence applications. Systolic array-based accelerators usually are used to accelerate the computation of DNNs. In a systolic array-based accelerator, many identical processing elements (PEs) are included. Testing it using typical scan and automatic test pattern generation (ATPG) technique is time consuming and not cost-effective. In this thesis, we propose a diagonally pipelined scan (DiPS) test scheme
for the systolic array-based accelerator. The DiPS test scheme generates test patterns at single PE and applies test patterns for all the PEs in a diagonally pipelined way. The features of the DiPS test scheme are low test complexity and scalability. The DiPS method can cover 100% delay fault of the multiply-and-accumulate circuit. The test application time complexity of the DiPS is (P × (S + 1) + S + m + n − 1) × 2 for an n × m PE array, where P and S denote the number of required test patterns and the scan chain length of a single PE, respectively. In comparison with the existing work, the test application time complexity with respect to the array size is reduced from (m + n) × P to (m + n − 1) × 2. Furthermore, we propose a fault location method based on the DiPS method. A faulty PE can be located by comparing the scan outputs of two adjacent PEs in the same diagonal. This reduces the number of test outputs of the PE array from n×m/2 to (m+n−2)/2. Finally, we design a built-in self-test and built-in self-repair (BISR) circuit for the systolic array-based PE array with a spare column. Assume that the error rate of a PE is between 0.1% and 1% for a 32x32 array size. The BISR scheme can gain 8.79% to 62.09% yield improvement. | en_US |
| DC.subject | 脈動陣列 | zh_TW |
| DC.subject | 測試 | zh_TW |
| DC.subject | 內建自我修復 | zh_TW |
| DC.subject | 自我測試 | zh_TW |
| DC.subject | 自我修復 | zh_TW |
| DC.subject | Systolic array | en_US |
| DC.subject | Testing | en_US |
| DC.subject | BISR | en_US |
| DC.subject | Self-test | en_US |
| DC.subject | Self-repair | en_US |
| DC.title | 應用於脈動陣列深度身經網路加速器之自 我測試與修復技術 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Built-In Self-Test and Repair Techniques for Systolic Array-Based AI Accelerators | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |