| dc.description.abstract | Generally, traditional GaN transistors use only one 2DEG channel formed AlGaN/GaN layer to conduct drain current. The use of multi-layer channel epitaxy also has structural limitations. In order to make the multi-layer channel transistor reach a positive threshold voltage, it is necessary to design the nanoscale fin width (WFin) for the gate to effectively control each channel. The research content of this paper is to discuss the gate recess tri-gate enhancement mode metal insulator semiconductor field effect transistor, with the epitaxial layer design of the AlGaN/GaN/AlGaN/GaN dual channel. Gate recess structure designed by the difference of etching depth, the change of transistor electrical properties, and threshold voltage to etching depth is confirmed by I-V measurement. With the Tri-gate structure design, several micron-level parallel grooves are etched at the gate position. A fin-shaped trench is designed to improve gate control ability. At the same time, the influence of the etching depth on the threshold voltage is discussed when the gate isolation etching depth is from 40 nm to 50 nm.
In the transistor process step, the device is fabricated by the argon ion implantation isolation method. After the device is isolated by argon ion implantation, ICP-RIE is used for trench and gate recess etching, the etching depth of the gate recess is 40, 45, and 50 nm, respectively. After etching, the etched surface will be cleaned with a certain proportion of BOE, HCl, and TMAH solutions, and then through ALD deposited 20 nm of aluminum oxide (Al2O3) as the gate insulating layer, and the final device had a trench width (WTrench) of 2 μm and a fin width of 2 μm.
The maximum drain current, on-resistance, maximum transconductance value, and the minimum subthreshold swing of the device without gate recess have better characteristics than other devices with gate recess. When the gate recess etching depth becomes deeper, the change of the threshold voltage increases. When the gate recess etching depth reaches 50 nm, a threshold voltage of 1.46 V, a drain current of 144.81 mA/mm, and an on-off current ratio of 4.52 108 V can be obtained. Through current and capacitance hysteresis measurement, the device interface trap density of each gate recess etching depth can be estimated, and the device is dipped in diluted BOE, HCl, and TMAH solutions to reduce the surface damages. The lowest interface trap density is about 7.86 1011 Ev-1cm-2 and a hysteresis voltage of 0.37 V. This study shows that the variation of the threshold voltage of the dual-channel device is smaller, which can be observed simultaneously from the simulation results of the dual-channel and single-channel devices. The variation of the threshold voltage of the dual-channel device is smaller than that of the single-channel device. | en_US |