| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 黃代佑 | zh_TW |
| DC.creator | Tai-Yu Huang | en_US |
| dc.date.accessioned | 2025-1-20T07:39:07Z | |
| dc.date.available | 2025-1-20T07:39:07Z | |
| dc.date.issued | 2025 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:444/thesis/view_etd.asp?URN=109521130 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 隨著資料密集型應用的快速發展，傳統的馮諾曼架構面臨記憶體牆問題。記憶體運算 (CIM) 架構是克服記憶體牆問題的一個很好的替代方案。CIM 架構可以以記憶體模式或運算模式運作。自旋轉移矩磁阻式隨機存取記憶體（STT-MRAM）是新興的非揮發性記憶體之一，被認為是實現 CIM 的良好候選者。為了減少 STT-MRAM 的寫入時間，提出了針對 MTJ 的替代寫入方案，即自旋霍爾輔助自旋轉移矩磁阻式隨機存取記憶體（SAS-MRAM）利用自旋軌道矩（SOT）機制來實現。本論文針對具有儲存和邏輯運算功能的基於 STT-MRAM 和 SAS-MRAM 的 CIM 進行了故障建模，並提出了March 測試來檢測儲存故障和運算故障。首先，透過為基於 1TIMTJ STT-MRAM 的CIM 架構注入單元內和單元間電氣缺陷來執行故障建模。定義了幾種記憶體和計算故障，包括靜態和動態故障。然後，提出了 18N March 測試演算法和（18 +4n1 + 2n2）N March 測試演算法來涵蓋靜態和動態故障。其次，透過為基於 2TIMTJ SAS-MRAM 的 CIM 注入單元內和單元間電氣缺陷來執行故障建模。定義了一個新的故障。然後，提出了一種 (13 +2n)N March 測試演算法來覆蓋基於 SAS-MRAM 的 CIM 的記憶體和計算故障。 | zh_TW |
| dc.description.abstract | With the rapid development of data-intensive applications, the conventional Von Neumann architecture suffers from the memory wall problem. Computing-in-memory (CIM) architecture is one good alternative to overcome the memory wall issue. CIM architecture can be operated in memory mode or computing mode. Spin-transfer torque magnetic random access memory (STT-MRAM) is one of the emerging non-volatile memories, which is considered as a good candidate to implement CIM. To reduce the STT-MRAM write time, alternative write scheme for MTJ is demonstrated that Spin-Hall-assisted Spin-Transfer Torque Magnetic Random Access Memory (SAS-MRAM) uses spin orbit torque (SOT) mechanism to implement. In this thesis, fault modeling is executed for STT-MRAM and SAS-MRAM-based CIMs with memory and logic operation functions, and March tests are proposed to detect memory faults and computing faults. First, fault modeling is executed by injecting intra-cell and inter-cell electrical defects for 1TIMTJ STT-MRAM-based CIM architecture. Several memory and computing faults are defined, including static and dynamic faults. Then, a 18N March test algorithm and a (18 + 4n1 + 2n2)N March test algorithm are proposed to cover static and dynamic faults. Second, fault modeling is executed by injecting intra-cell and inter-cell electrical defects for 2TIMTJ SAS-MRAM based CIMs. One new fault is defined. Then, a (13 + 2n)N March test algorithm is proposed to cover memory and computing faults of SAS-MRAM-based CIMs. | en_US |
| DC.subject | 自旋轉移矩磁阻式隨機存取記憶體 | zh_TW |
| DC.subject | 運算記憶體 | zh_TW |
| DC.subject | 測試 | zh_TW |
| DC.subject | STT-MRAM | en_US |
| DC.subject | Computing-In-Memories | en_US |
| DC.subject | Testing | en_US |
| DC.title | 基於自旋轉移矩磁阻式隨機存取記憶體之運算記憶體測試 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Testing of STT-MRAM-Based Computing-In-Memories | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |