| dc.description.abstract | In microwave and millimeter-wave receiver systems, the Low Noise Amplifier (LNA) is a crucial integrated circuit at the front end. The primary function of the LNA is to amplify signals received by the antenna before transmitting them to the subsequent circuits. In addition to basic requirements such as gain and noise figure, low power consumption and high linearity are also design goals. In microwave transmitter systems, the Power Amplifier (PA) is another key circuit. With the development of fifth-generation communication, the demand for high-output power amplifiers in the millimeter-wave frequency band is gradually increasing. Amplifiers with high output power, high linearity, and wide bandwidth have been proposed. Power amplifiers are typically the most power-consuming components in transmitter systems, so designing them with lower DC power consumption and a more compact footprint is a trend.The research objectives of this thesis focus on achieving low power consumption, high gain, and high linearity for LNAs, primarily designed for the K-band and Ka-band using CMOS technology. For power amplifiers, the research goal is to achieve broadband performance, also designed for the K-band and Ka-band using CMOS technology.
Chapter 2 introduces a low noise amplifier designed using TSMC 90 nm process, operating in the Ka-band. To achieve low power consumption and high gain, a transconductance-boosting architecture and neutralization with stable capacitor architecture were employed to increase stability while improving gain. Current reuse architecture was used to reduce power consumption, implemented in a two-stage structure. The circuit achieved a maximum gain of 7.5 dB, a minimum noise figure of 4.9 dB, and a chip area of 0.37 mm2.
Chapter 3 presents a low noise amplifier designed using TSMC 0.18 µm process, operating in the K-band. The design utilizes a dual transformer architecture to enhance gain, source degeneration inductor to reduce noise figure, and an external bias on the transistor′s Body terminal to improve linearity. Additionally, a current reuse architecture was employed to reduce power consumption, implemented in a two-stage stacked structure. The circuit achieved a maximum gain of 18.2 dB, a minimum noise figure of 5.7 dB, and a chip area of 0.53 mm2.
Chapter 4 introduces power amplifiers designed using TSMC 0.18 µm and TSMC 90 nm processes. The power amplifier designed with TSMC 0.18 µm operates in the K-band, utilizing a transformer architecture to achieve broadband gain. The circuit, composed of a two-stage stacked structure, achieved a maximum gain of 19 dB, a 3 dB bandwidth from 20 GHz to 26.1 GHz, 1 dB compression point of 12.4 dBm, saturation output power of 16.1 dBm, and a third-order output intercept point of 26 dBm. The chip area is 0.53 mm2. The power amplifier designed with TSMC 90 nm operates in the Ka-band, employing a neutralization with stable capacitor architecture to enhance gain and stability, configured in a four-way stacked structure. The circuit achieved a maximum gain of 12.5 dB, a 3 dB bandwidth from 28.3 GHz to 42.6 GHz, 1 dB compression point of 9.2 dBm, saturation output power of 18 dBm, and a third-order output intercept point of 20 dBm. The chip area is 0.49 mm2.
Finally, Chapter 5 concludes the thesis. | en_US |