| DC 欄位 |
值 |
語言 |
| DC.contributor | 機械工程學系 | zh_TW |
| DC.creator | 林冠宇 | zh_TW |
| DC.creator | Guan-Yu Lin | en_US |
| dc.date.accessioned | 2023-6-14T07:39:07Z | |
| dc.date.available | 2023-6-14T07:39:07Z | |
| dc.date.issued | 2023 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:444/thesis/view_etd.asp?URN=110323051 | |
| dc.contributor.department | 機械工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 本研究提出了一種對 N 型碳化矽加速蝕刻的方法，在碳化矽與陽極銅片之間放置了 P 型矽晶圓形成 PN 接面，施加電場後，能夠驅動 P 型矽晶 圓中的主要載流子(電洞)到 N 型碳化矽當中以加速電化學蝕刻。陰極電極為白金片，並且蝕刻液為氫氟酸 (49.5%) 與乙醇 (99.5%) 以體積比 1:1 調製，再分別以不同的摻雜濃度的 P 型矽晶圓對其進行電化學蝕刻。碳化矽在經過電化學蝕刻後會產生分層現象產生薄膜，由 SEM 的圖像可以得知，碳化矽在經過蝕刻後，孔隙率與蝕刻速率會隨著試片摻雜濃度的不同而有所改變。在使用 PN 接面蝕刻碳化矽的實驗中，發現了試片有未產生分層現象的部分，對其表面結構進行分析，發現了蝕刻會傾向於往碳化矽 表面拋光產生的划痕(缺陷)進行，且在 SEM 剖面圖當中得知未分層蝕 刻速度快於已分層的部分。在 I-V 圖中，電壓會有上升的情形，因為在蝕 刻過程中碳化矽表面所產生的薄膜形成了近似電容的效應，導致電流無法 流通造成電阻上升減慢了蝕刻速度，而利用 PN 接面蝕刻可改善此情況。 從 TEM、XRD 可知碳化矽在蝕刻後晶格不會有改變，EDS 可知碳化矽在 蝕刻後元素無太大變化，PL 則顯示出了未分層結構有藍移的情形發生。 | zh_TW |
| dc.description.abstract | This study proposes a method for accelerated etching of N-type silicon carbide. P-type silicon wafer is placed between the silicon carbide and the anode copper plate to form a PN junction. Applying an electric field can drive the primary carrier (holes) in the P-type silicon wafer into the N-type silicon carbide to accelerate electrochemical etching. The cathode electrode is a platinum plate, and the etching solution is a mixture of hydrofluoric acid (49.5%) and ethanol (99.5%) in a volume ratio of 1:1. After electrochemical etching, the silicon carbide undergoes layering to produce a thin film. SEM images showed that the porosity and etching rate of SiC changed with the doping concentration of the samples. The etching rate also increases as the doping concentration of the P-type silicon wafer increases. In the experiment of etching silicon carbide using a PN junction, some parts of the sample did not undergo layering. Analysis of the surface structure revealed that etching tended to occur at scratches (defects) generated by polishing the silicon carbide surface. In the I-V curve, the voltage increases due to the formation of a thin film on the silicon carbide surface during the etching process. However, using a PN junction for etching can improve this situation. TEM and XRD analyses revealed that the crystal lattice of silicon carbide did not change after etching, and EDS showed that there was no significant change in the elements of the silicon carbide after etching. PL revealed a blue shift in the non- layered structure. | en_US |
| DC.subject | 碳化矽 | zh_TW |
| DC.subject | 電化學蝕刻 | zh_TW |
| DC.subject | PN接面 | zh_TW |
| DC.subject | 多孔結構 | zh_TW |
| DC.subject | Silicon carbide | en_US |
| DC.subject | Electrochemical etching | en_US |
| DC.subject | PN junction | en_US |
| DC.subject | Porous structure | en_US |
| DC.title | PN 接面輸入電洞以電化學蝕刻 N 型碳化矽之研究 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Inputting the hole Induced by PN Junction to Electrochemically Etch N-type Silicon Carbide | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |