| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 詹宜庭 | zh_TW |
| DC.creator | Yi-Ting Chan | en_US |
| dc.date.accessioned | 2024-7-26T07:39:07Z | |
| dc.date.available | 2024-7-26T07:39:07Z | |
| dc.date.issued | 2024 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:444/thesis/view_etd.asp?URN=110521007 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 鎖相迴路用於產生高品質的時脈訊號，而加入次諧波注入技術將具有抑制振盪器高頻相位雜訊的特性，但是也同時面臨若注入時序不佳將嚴重影響電路效能的問題將造成參考突波 (Reference spur)及時脈抖動 (Jitter)的惡化。因此本論文提出操作於2.4GHz以單一複製延遲單元實現次諧波注入時序校正之注入式鎖相迴路具有額外的迴路自適應校正注入時序到最佳注入位置。並複製環形振盪器中的延遲單元，在校正過程中，以此單級複製延遲單元和注入脈波進行相位比較。區隔了受到注入及進行相位比較的延遲單
元。額外耗費少量的功率消耗及硬體面積便能達到更準確的注入位置，提升電路效能。電路設計與佈局以90nm CMOS製程實現。輸出時脈頻率為2.4GHz、參考時脈訊號為150MHz。完成次諧波注入時序校正後，次諧波注入式鎖相迴的參考突波為-44.3dBc輸出相位雜訊下為-115.0dBc/Hz @ 1MHz offset；方均跟抖動為970fs；不含輸入與輸出緩衝器的電路功率消耗為7.3mW核心電路面積為0.063 mm2，晶片面積為0.912 mm2。 | zh_TW |
| dc.description.abstract | Phase-locked loop (PLL) is used to generate high-quality clock signals, and incorporating sub-harmonic injection technology will have the characteristic of suppressing high-frequency phase noise of the oscillator. However, it also faces the problem of severely affecting circuit performance if the injection timing is poor, such as degradation in metrics like Reference spur and Jitter. Therefore, this paper proposes an injection-locked phase-locked loop with single replica delay cell sub-harmonically injection timing calibration operating at 2.4GHz, featuring additional loop-adaptive calibration to optimize injection timing to the best position. It duplicates delay units within the ring oscillator, and during the calibration process, it compares phases with this single replica delay cell and injection pulse. This segregates the delay cells affected by injection and those used for phase comparison. Achieving a more accurate injection position requires only a small additional power consumption and hardware area, thereby enhancing circuit performance.
The circuit design and layout are implemented using a 90 nm CMOS process. The output clock frequency is 2.4GHz, and the reference clock signal is 150MHz. After completing the sub-harmonically injection timing calibration, the reference spur of the sub-harmonic injection-locked loop is -44.3 dBc; output phase noise is -115.0 dBc/Hz @ 1MHz offset; root mean square (RMS) jitter is 970fs; circuit power consumption without input and output buffers is 7.3 mW; core circuit area is 0.063 mm2, and the chip area is 0.912 mm2. | en_US |
| DC.subject | 鎖相迴路 | zh_TW |
| DC.subject | 次諧波注入技術 | zh_TW |
| DC.subject | 次諧波注入式鎖相迴路 | zh_TW |
| DC.subject | 注入時序校正 | zh_TW |
| DC.subject | 單一複製延遲單元 | zh_TW |
| DC.subject | 環形振盪器 | zh_TW |
| DC.subject | Phase-Locked Loop | en_US |
| DC.subject | Sub-harmonically Injection locked | en_US |
| DC.subject | Sub-harmonically Injection locked PLL | en_US |
| DC.subject | Injection Timing Calibration | en_US |
| DC.subject | Single Replica Delay Cell | en_US |
| DC.subject | Ring-based Oscillator | en_US |
| DC.title | 以單一複製延遲單元實現次諧波注入時序校正之注入式鎖相迴路 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | An Injection-locked Phase-locked Loop with Single Replica Delay Cell Sub-Harmonically Injection Timing Calibration | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |