| dc.description.abstract | In recent years, as data transmission rates have continuously increased, the channel′s low-pass filter characteristics have caused significant signal attenuation after transmission. This leads to inter-symbol interference (ISI) and signal integrity issues, making it difficult for the receiver to correctly interpret the data. As a result, downstream circuits may malfunction, and the bit error rate (BER) may increase. The role of an equalizer is to compensate for high-frequency attenuation caused by the transmission channel, ensuring the data can be accurately interpreted. Additionally, to adapt the equalizer to various levels of channel attenuation, an adaptive mechanism is incorporated, allowing it to automatically detect and provide optimal compensation based on the channel′s attenuation characteristics.
In traditional adaptive systems, differential data signals are typically compared to determine their logic states. However, when the transmission channel experiences severe attenuation, even after initial compensation by a continuous-time linear equalizer (CTLE), the data logic may remain difficult to discern. This can cause downstream circuits to malfunction or the adaptive system to converge to an incorrect state, leading to improper compensation.
This study proposes an adaptive equalizer for high loss channels, capable of handling attenuation ranging from -11.40 dB to -31.91 dB. It also introduces a Combinational Data Pattern Detector (CB-DPD), which can accurately identify data patterns for zero-forcing algorithm even under severe attenuation and provide the optimal compensation for the data.
The proposed design is implemented using the TSMC 90 nm (TN90GUTM) 1P9M CMOS process. The circuit operates at 1V, inupt 8 Gbps NRZ data signals encoded with PRBS7, and uses a 4 GHz clock. The equalizer compensates for channel attenuation within a range of -11.40 dB to -31.91 dB. Post-layout simulation results show an eye height of 406.86 mV and an eye width of 110.92 ps for short channels, while for long channels, the eye height is 120.61 mV and the eye width is 79.38 ps. Furthermore, the proposed CB-DPD increases the output eye height by 58.74% compared to conventional DPD.The total power consumption is 21.70 mW, with the equalizer consuming 9.02 mW (41.57%) and the adaptive system consuming 12.68 mW (58.43%). The chip area is 1.13 mm2, with a core circuit area of 0.079 mm2. | en_US |