博碩士論文 110521012 完整後設資料紀錄

DC 欄位 語言
DC.contributor電機工程學系zh_TW
DC.creator蘇姿羽zh_TW
DC.creatorTzu-Yu Suen_US
dc.date.accessioned2024-10-22T07:39:07Z
dc.date.available2024-10-22T07:39:07Z
dc.date.issued2024
dc.identifier.urihttp://ir.lib.ncu.edu.tw:444/thesis/view_etd.asp?URN=110521012
dc.contributor.department電機工程學系zh_TW
DC.description國立中央大學zh_TW
DC.descriptionNational Central Universityen_US
dc.description.abstract近年隨著先進製程的演進以及產品應用上的需求,資料在傳輸速率方面也跟著大幅提升,現今傳輸介面上,已由高速串列傳輸主導,例如:PCI Express、Ethernet、USB及HDMI等。然而當資料速率不斷提升,即位元週期不斷縮小下,抖動對於資料的佔比將更加嚴重,並且電路的時間餘裕也將越來越限縮,導致抖動容忍度惡化以及誤碼率提升,因此如何降低追鎖抖動以及改善抖動容忍度在電路設計上至關重要。 本論文遵循USB 3.2 Gen1的通訊規範,實現一個具自適應且多階資料獨立相位追蹤補償技術之5 Gbps半速率時脈與資料回復電路。zh_TW
dc.description.abstractIn recent years, with the advanced process technology and the increasing demand for product applications, data transmission rates have significantly increase. Nowadays, high-speed serial link has become dominant in transmission interfaces, such as PCI Express, Ethernet, USB, and HDMI. However, as data rates continue to increase and unit interval continue to shrink, jitter becomes the significant issue, and the timing margin in circuits become increasingly constrained, leading to worse jitter tolerance and higher bit error rate. Therefore, reducing hunting jitter and improving jitter tolerance are crucial in circuit design. This thesis adheres to the USB 3.2 Gen1 communication specification and implements a 5 Gbps half-rate clock and data recovery circuit with adaptive and multi-level data independent phase tracking compensation technology.en_US
DC.subject時脈與資料回復電路zh_TW
DC.subjectCDRen_US
DC.title具自適應且多階資料獨立相位追蹤補償技術之 5 Gbps 半速率時脈與資料回復電路zh_TW
dc.language.isozh-TWzh-TW
DC.titleA 5 Gbps Half-Rate Clock and Data Recovery with Adaptive Multi-level Data Independent Phase Tracking Compensation Techniqueen_US
DC.type博碩士論文zh_TW
DC.typethesisen_US
DC.publisherNational Central Universityen_US

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