| dc.description.abstract | With the advancement of semiconductor technology driven by Moore′s Law, computational power has increased, energy consumption has decreased, and manufacturing costs have been reduced. These developments have led to innovative applications of electrical equipment in human society. When chips and circuit boards become sufficiently small, devices achieve adequate battery life, and prices become affordable to the majority, the technological singularity of development—namely the Fourth Industrial Revolution—is reached. This revolution focuses on the interconnectivity of wearable devices, automation of electronic products, machine learning, and real-time data transmission. Through algorithms, control engineering, and mechanical systems, automation monitoring and data analysis are realized, breaking traditional boundaries and fostering innovation.
In recent years, industrial control equipment, such as industrial automation inverters, AC servo motor controllers, and power regulators for renewable energy, has increasingly required isolation between voltage sources on both sides to ensure equipment safety. Among these components, isolation amplifiers embedded in chips play a critical role. These amplifiers must balance considerations of transmission speed, power consumption, and maximum isolation voltage. This thesis sets the transmission speed based on the overall system, integrates the isolation components within the chip to reduce area, and aims to minimize power consumption.
This thesis implements a circuit architecture for magnetic coupling isolation systems, primarily consisting of two parts: a transformer-based magnetically coupled digital isolation amplifier and a clock data recovery (CDR) circuit. The digital isolation amplifier is based on the pulse polarity architecture, offering advantages such as smaller transformer area and lower power consumption. The detailed circuit design includes edge detectors for detecting rising and falling edges, current-limiting inverters to suppress counter-pulses that may cause logic errors, and a transformer constructed by stacking spiral inductors using Metal 6 and Metal 4 layers. A lumped circuit model is employed to analyze the transformer′s parasitics, while high-speed pulse detectors and comparators are used to recover digital signals.
The CDR circuit comprises a phase detector, charge pump, loop filter, and voltage-controlled oscillator (VCO). For relatively low-speed environments, a Hogge phase detector is adopted to meet the requirements, and a dual-path charge pump loop filter is utilized to reduce the area of the capacitive components within the filter.
The circuit is fabricated using TSMC’s 0.18 μm CMOS 1P6M process, with a chip area of approximately 0.810 mm2. The supply voltage is 1.8 V, and the total circuit power consumption is 21.83 mW. The circuit achieves a transmission speed of 28.8 Mbps, with an inductor diameter of 276 μm, an isolation voltage of 170 V, transient common-mode noise immunity (CMTI) of 35 kV/μs, a lock time of 24.2 μs, and clock jitter of 28.12 ps. | en_US |