| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 楊云緯 | zh_TW |
| DC.creator | Yun-Wei Yang | en_US |
| dc.date.accessioned | 2024-3-12T07:39:07Z | |
| dc.date.available | 2024-3-12T07:39:07Z | |
| dc.date.issued | 2024 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:444/thesis/view_etd.asp?URN=110521032 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 晶片佈局規劃是晶片設計的關鍵步驟，決定了在晶片畫布上放置模組的位置。一個良好的佈局方案可以最小化連接晶片上不同模組所需的總線長度。更短的總線長度意味著訊號延遲更小、功耗更低，從而導致晶片運行更快、更有效率。然而考量到現今的晶片通常包含數十億個電晶體，且布局的結果會大大的影響擺置與繞線的進行，因此採用傳統演算法如貪婪演算法或啟發式演算法的布局策略，通常難以找到最優解。強化學習（RL）提供了一種有希望的方法來解決這些限制。它透過試誤和獎勵進行學習，調整策略以找到最佳解決方案。這使得它非常適合解決諸如佈局規劃之類的複雜最佳化問題。
本研究介紹了FusionPlanner，這是一種新穎的模型，有效地利用了本地和全局信息，自主創建有效的晶片佈局設計。其性能可以超越或匹配最近先進方法的水平。它具有許多吸引人的優點，在以前的工作中是不存在的。首先，以往的晶片佈局規劃工作通常集中在硬模塊(Hard macros)上。我們的工作透過考慮軟模組和硬模塊的面積和連接性，解決了佈局軟模組的挑戰。這使我們能夠產生更準確的佈局圖，考慮到軟模塊(Soft modules)選項的全部範圍，並防止與硬模塊的任何重疊。其次，我們的工作採用了基於圖的網路訓練方法，並著重於邊緣特徵的有效整合。我們的方法結合了影像特徵以捕捉局部訊息，以及圖形特徵以掌握全局資訊。這種綜合方法旨在增強對局部細節的感知，同時在影像內捕捉更廣泛的上下文理解。
我們的實驗表明，我們的研究提出了一個可以改善28奈米工業設計晶片佈局總線長度的方法。此外，我們的研究可以透過在設計過程的早期考慮軟模組，來減少晶片佈局的設計時間。 | zh_TW |
| dc.description.abstract | Chip floorplanning is a crucial step in chip design, determining the placement of modules on the chip canvas. A good floorplan minimizes the total wirelength of connections to different modules on the chip. Shorter wires imply less signal delay and lower power consumption, leading to faster and more efficient chip operation. However, considering the modern ICs with millions of transistors, conventional greedy-based or heuristic-based floorplan algorithms often leads to sub-optimal solutions. Reinforcement learning (RL) offers a promising approach to addressing these limitations. It learns through trial and error and guides by rewards, adapting its strategy to find the best solution. This makes RL suitable for tackling complex optimization problems like floorplanning.
This thesis introduces FusionPlanner, a novel model that effectively leverages both local and global information to autonomously create a valid chip layout design. Its performance can surpass or match state-of-the-art methods. It possesses numerous attractive advantages that are absent in previous works. Firstly, previous works on chip floorplanning have typically focused on hard macros. Our work addresses the challenges of handling soft modules by considering the area and connectivity of both soft modules and hard macros. This allows us to produce more accurate floorplans that take into account the full range of soft module options and prevent any overlap with hard macros. Secondly, our work uses a graph-based network training approach that focuses on the effective integration of edge features. Our method combines image features to capture local information and graph features to grasp global information. This integrated approach aims to enhance the perception of local details while capturing a more extensive contextual understanding within the image.
Our experiments demonstrate that our floorplan method can successfully improve the total wirelength of industrial designs with 28nm technology. In addition, our work can reduce the design time of chip floorplanning by considering soft modules earlier in the design process. | en_US |
| DC.subject | 強化式學習 | zh_TW |
| DC.subject | 布圖規劃 | zh_TW |
| DC.subject | 實體設計 | zh_TW |
| DC.subject | Reinforcement learning | en_US |
| DC.subject | Floorplan | en_US |
| DC.subject | Physical design | en_US |
| DC.title | 基於強化學習的晶片佈局規劃的卷積神經網路與圖神經網路融合架構 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | FusionPlanner: A CNN-GNN Fusion Architecture for Reinforcement Learning-based Floorplanning | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |