| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 黃韶翊 | zh_TW |
| DC.creator | SHAO-YI HUANG | en_US |
| dc.date.accessioned | 2024-7-1T07:39:07Z | |
| dc.date.available | 2024-7-1T07:39:07Z | |
| dc.date.issued | 2024 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:444/thesis/view_etd.asp?URN=110521041 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 在數位時代，真隨機數對於加密和通訊至關重要。傳統的真隨機數生成器依賴
於物理現象，如熱噪音或量子效應，通常需要昂貴的硬件。本研究探討了 CMOS 設
備閾值電壓（Vth）的固有變化，以生成高質量的隨機數，提供了一種適用於嵌入
式系統的成本效益高的替代方案。
我們提出了 40 奈米邏輯 CMOS 技術和 1T 單元，來創建一個 1k-bits 的 TRNG
陣列。這利用 Vth 的微小電性變化作為熵源。TRNG 陣列的加密參數在不同溫度下
進行了測試，評估其對安全應用的適用性。
實驗使用了四種閾值電壓類型：Hvt 通道長度 40nm(hvt_40nm)、Svt 通道長度
45nm(svt_45nm)、Svt 通道長度 40nm(svt_40nm)和 Lvt 通道長度 40nm(lvt_40nm)，每種單
元形成一個 1k-bits 的 TRNG 陣列。這些設置成功地生成了 50％概率的隨機數，操
作速度高（10ns），並且能耗低（8.5pJ/bit）。一個 p 型 MOSFET 做為一個單元，
該設計每個單元面積僅為 0.1734um2，突顯了其在隨機數生成方面的競爭價值。 | zh_TW |
| dc.description.abstract | In the digital era, the true random numbers are crucial, especially in encryption and
communication. Traditional true random number generators, relying on the phenomena, such
as the thermal noise, often require the expensive hardware. This study explores inherent
variations in the gate threshold-voltage (Vth) of the CMOS devices to generate high-quality
random numbers, providing a cost-effective alternative suitable for embedded systems.
We propose the 40nm logic CMOS technology and 1T cells to create a 1-kbit TRNG Array.
This utilizes small electrical variations of the Vth as the entropy source. The TRNG Array′s
cryptographic parameters were tested under various temperatures, assessing its suitability for
secure applications.
The experiment used four types of the threshold voltages: the hvt_40nm, svt_45nm,
svt_40nm, and lvt_40nm, each FORMing a 1-kbit TRNG Array. These SETups successfully
generated random numbers with a 50% probability, operated at high speeds (10-ns operation
time), and required low power (8.5pJ/bit). The compact design features a 0.1734-um2
area
per cell with one p-type MOSFET, highlighting its competitive value in random number
generation. | en_US |
| DC.subject | 記憶體 | zh_TW |
| DC.title | 高速、低能耗、微型1T-PMOS TRNG陣列的設計和特性描述 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Design and Characterization of High-speed Low- energy consumption Ultra-scaled 1T-PMOS TRNG Array | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |