| dc.description.abstract | This paper primarily investigates the use of a switched-capacitor array and waveform shaping to achieve a local oscillator with lower phase noise. Chapter 2 focuses on a K and Ka-band voltage-controlled oscillator (VCO) using a 5-bit switch-capacitor array to achieve high frequency tuning range. Chapter 3 first discusses the impact of waveform shaping on phase noise, and introduces X-band Class-F23 voltage-controlled oscillator. Additionally, it proposes three ways to realize Class-F23 quadrature voltage-controlled oscillators(QVCO), each utilizing back-gate coupling, gate capacitance coupling, and drain capacitance coupling, respectively. Chapter 4 focuses on implementing an X-band Class-F23 quadrature phase-locked loop (PLL) using the X-band quadrature voltage-controlled oscillator with drain capacitance coupling as the oscillator source in Chapter 3.
Chapter 2 is talking about a K/Ka-band 5-bit VCO, which using switch-capacitor array and switchable varactor array. The first half of chapter primarily focuses on the design of multi-bit switch-capacitor arrays and switchable varactor array. First, it metions the impact of the KVCO on phase noise and phase-locked loop stability. When the KVCO is small, the utilization of a switch-capacitor array becomes necessary to maintain a high tuning range, additionally, due to the small KVCO, so I designed auxiliary switchable varactor to ensure frequency continuity. The circuit topology is the fundamental cross-coupled pair with 5-bit switch-capacitor array and switchable varactor array to realize a voltage-controlled oscillator. This circuit is fabricated in TSMC 90 nm CMOS process. The frequency tuning range is from 22.6 to 29.8 GHz(27.5%), the overall output power is from -6 to -7.7 dBm, the overall phase noise at 1 MHz offset frequency is from -98 to -103.5 dBc/Hz, the FoMPN is from -184 to -184.4 dBc/Hz, the FoMT is from -192.8 to -193.1 dBc/Hz, the chip size is 0.94 × 0.81 mm2. The second half of Chapter 2 focuses on explaining how to design bit numbers quickly according to industry design specifications, using experience and formula calculations. It also provides a simulated example using TSMC 22 nm CMOS process.
Chapter 3 is about the design of an X-band Class-F23 quadrature voltage-controlled oscillator. From the time-variant model, we know that shaping the output waveform into a square wave is necessary to achieve better phase noise, which corresponds to an Class-F voltage-controlled oscillator. Additionally, due to the Groszkowski effect, we need to realize a high-impedance at twice the frequency to reduce waveform asymmetry and improve phase noise. Therefore, the final choice is to implement the Class-F23 voltage-controlled oscillator. First, we design a Class-F23 voltage-controlled oscillator. Then, based on the designed voltage-controlled oscillator, we implement a quadrature voltage-controlled oscillator of the Class-F23 using methods such as back-gate coupling, gate capacitance coupling, and drain capacitance coupling, respectively. This circuit is fabricated in TSMC 0.18 μm CMOS process. After the measurment and comparison, we know that the Class-F23 quadrature voltage-controlled oscillator with drain capacitance coupling exhibited better circuit performance. The frequency tuning range is from 10.23 to 10.89 GHz, the overall output power is from -6 to -8 dBm, the overall phase noise at 1 MHz offset frequency is from -110.5 to -113.8 dBc/Hz,the FoMPN is from -181.1 to -184.5 dBc/Hz, the FoMT is from -176.8 to -180.2 dBc/Hz, the FoMQ is from -202 to -228.7 dBc/Hz, the chip size is 0.725 × 1.127 mm2.
Chapter 4 introduces the X-band Class-F23 quadrature phase-locked loop. This chapter will discuss the functions and operating theory of each sub-circuit in the PLL. Furthermore, it will analyze the stability and spur suppression ability of the PLL. The voltage-controlled oscillator in the loop utilizes the quadrature voltage-controlled oscillator with drain capacitance coupling which introduced in Chapter 3. This circuit is fabricated in TSMC 0.18 μm CMOS process. The VCO frequency tuning range is from 10.51 to 11.06 GHz,and the PLL frequency locking range is from 10.52 to 11.06 GHz, almost full frequncy band locking, the phase noise at 1 MHz offset frequency is -104 dBc/Hz. Under the integration range of 1 kHz to 40 MHz, the measured minimum root mean square jitter is 250 fs. The spur suppression throughout the entire frequency band is greater than 60 dBc. The FoMPN is -166.5 dBc/Hz, the FoMjitter is -233.7 dB, the FoMN is -251.7 dB, the chip size is 1.05 × 1.614 mm2. | en_US |