| dc.description.abstract | 3D NAND flash memory chips have been continuously advancing in terms of capacity and read/write speed, leading to shorter product life cycles. This necessitates chip manufacturers to allocate more resources to reduce firmware development and testing/validation time. To address this, we have developed a testing platform specifically designed for 3D NAND flash memory. The platform aims to automatically generate and output firmware code for functional instructions and program scripts for test procedures based on the specifications of the target chip. This enables users to quickly configure functional instructions and analyze memory characteristics, while ensuring efficient program development and improved reliability. The platform verifies the correctness of basic functional instructions (such as erase, program, read, and read retry) in TLC mode and conducts feature testing in TLC, SLC, and mixed TLC/SLC modes. Additionally, it utilizes experiments to validate durability in different modes. Using this platform, we conducted a series of tests on 3D NAND flash memory. In TLC mode, after performing 3,000 P/E cycles on WL0 and WL1, the read count of WL1 with Close WL was found to be 1.23 times higher compared to WL0 without Close WL, until a fatal error occurred during read. Furthermore, beyond 3,000 P/E cycles, regardless of Close WL, the overall read count of WL0 was higher than WL1 when reading until a fatal error occurred. This demonstrates the significant impact of P/E cycles on the read count of the memory. These findings validate the practicality of the developed testing platform for 3D NAND flash memory. | en_US |