| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 唐儷綾 | zh_TW |
| DC.creator | Li-Ling Tang | en_US |
| dc.date.accessioned | 2025-1-17T07:39:07Z | |
| dc.date.available | 2025-1-17T07:39:07Z | |
| dc.date.issued | 2025 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:444/thesis/view_etd.asp?URN=111521026 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 隨著神經網路的複雜度日益增加，乘加運算（Multiply-Accumulate, MAC）在計算效率和能耗表現方面扮演著關鍵角色。基於壓縮器的MAC架構以其高效能與低功耗著稱，但由於乘法器與累加器階段間的進位信號（carry-out, cout）傳遞，經常導致延遲瓶頸和吞吐量下降，限制了其潛力。
為解決這些挑戰，我們提出了一種進位信號替換架構（Carry-Out Replacement Architecture），這是一種整合分段處理與優化累加器結構的新型MAC設計。透過新增寄存器來暫存cout信號，該架構將進位的累加延遲至後續階段，有效縮短了關鍵路徑。此分段策略平衡了管線階段的延遲，同時將額外寄存器帶來的開銷降至最低。此外，我們採用了寄存器整合策略（Register Integration Strategy），以選擇性地優化特定的cout信號，從而在給定的延遲限制下提升效率。
實驗結果證實了進位信號替換架構的有效性，在多項性能指標上展現了顯著的改善。僅使用進位信號替換架構，即可在效能每瓦（TOPS/W）方面比最先進的基於壓縮器的MAC架構提升5.45%。結合寄存器整合策略後，該架構的效能每瓦提升幅度最高可達19.58%。此外，與基準設計相比，此架構在功耗方面減少了8.77%，在面積方面減少了13.41%。這些結果顯示，進位信號替換架構在高性能MAC密集型應用中具有出色的適應性與效率，為下一代神經網路加速器提供了穩健的解決方案。 | zh_TW |
| dc.description.abstract | As neural networks grow increasingly complex, Multiply-Accumulate (MAC) operations are crucial for ensuring computational efficiency and energy performance. Compressor-based MAC architectures are known for their high speed and low power consumption, but their potential is often limited by the propagation of carry-out (cout) signals across multiplier and accumulator stages, resulting in latency bottlenecks and reduced throughput.
To overcome these challenges, we present carry-out replacement architecture, a novel MAC design that integrates segmented processing and optimized accumulator structures. By incorporating additional registers to temporarily store cout values, carry-out replacement architecture defers their accumulation to subsequent stages, effectively shortening the critical path. This segmentation strategy balances delay across pipeline stages while minimizing the overhead introduced by additional registers. Additionally, a register integration strategy is employed to selectively optimize specific cout signals, enhancing efficiency under defined delay constraints.
Experimental results validate the effectiveness of carry-out replacement architecture, demonstrating substantial improvements across multiple performance metrics. Without the register integration strategy, carry-out replacement architecture achieves a 5.45% increase in TOPS/Watt compared to the optimized compressor-based MAC architectures. When the register integration strategy is applied, the Carry-Out Replacement Architecture achieves up to a 19.58% improvement in TOPS/Watt. Furthermore, the architecture achieves an 8.77% reduction in power consumption and a 13.41% reduction in area compared to baseline designs. These results highlight the adaptability and efficiency of carry-out replacement architecture for high-performance MAC-intensive applications, making it a robust solution for next-generation neural network accelerators. | en_US |
| DC.subject | 以壓縮器為基礎的乘加器 | zh_TW |
| DC.subject | 關鍵路徑 | zh_TW |
| DC.subject | 吞吐量 | zh_TW |
| DC.subject | 高速 | zh_TW |
| DC.subject | 低功率 | zh_TW |
| DC.title | 透過基於壓縮器的MAC進位輸出替換架構提升系統計算吞吐量與能效 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Enhancing Computational Throughput and Power Efficiency in Compressor-Based MAC via Carry-Out Replacement Architecture | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |