| dc.description.abstract | Improving the blocking voltage of GaN-on-Si devices is an important design consideration. In this experiment, a relatively thick (6.5 μm) carbon-doped buffer layer was used as part of the epitaxial structure, grown on a low-resistivity silicon substrate. By estimating the gate-drain distance (LGD) dimension and formula derivation, the relationship between device size and blocking voltage was observed. Using Silvaco TCAD simulation, the electrical characteristics and blocking voltage prediction of devices with different gate-drain distances were analyzed. Enhancement-mode GaN gate transistors were then fabricated on this epitaxial structure for measurement and analysis. The impact of different buffer layer thicknesses on the blocking voltage was investigated, in order to understand the relationship between the GaN-on-Si epitaxial buffer layer and the blocking voltage specifications, and to obtain the appropriate device structure and reduce manufacturing costs.
p-GaN gate AlGaN/GaN HEMTs devices with different gate-drain distances were measured for off-state blocking voltage under silicon substrate conditions. When LGD = 8 μm, the device exhibited a blocking voltage of 1298 V at a drain leakage current of 1 mA/mm, and when LGD = 11 μm, the blocking voltage was 1742 V, with corresponding specific on-resistance (RON,SP) values of 1.55 mΩ·cm2 and 1.77 mΩ·cm2, respectively. By observing the drain, gate, and vertical substrate leakage currents, it was found that for the LGD = 8 μm design, the primary limitation on blocking voltage was not the vertical buffer substrate leakage current, likely due to the short gate-drain distance. In contrast, for the LGD = 11 μm design, the vertical buffer substrate leakage current became the main limiting factor for the blocking voltage. Previous experiments also confirmed that for devices with LGD larger than 11 μm, the vertical buffer substrate leakage current was the primary limitation for the blocking voltage.
Although this experiment primarily used a 6.5 μm carbon-doped buffer layer, Silvaco TCAD simulations were ultimately performed to analyze the impact of different buffer layer thicknesses on the blocking voltage. Using the same device structure design (LGD = 8 μm) and maintaining a 1200 V blocking voltage, the study was conducted for various buffer layer thicknesses. The simulation results showed that the buffer layer thickness could be reduced from the 6.5 μm used in this experiment to 4.5 μm, while still achieving a 1251 V blocking voltage at a drain leakage current of 1 mA/mm. | en_US |