| dc.description.abstract | This thesis mainly focuses on the design and analysis of power amplifiers. We use the TSMC 90-nm CMOS process and WIN 100-nm GaAs pHEMT process to implement various power amplifier architectures.
In Chapter 2, we continue the work of previous lab members and redesign a power amplifier using the TSMC 90-nm CMOS process, operating at a center frequency of 40 GHz in the Q-Band. This circuit is a differential architecture, using transformers at the input and output for matching, and to achieve single-ended to differential signal conversion. We used neutralization capacitor technology to achieve optimal stability and maximum available gain, and employed a cascode architecture to increase the operating voltage, thereby enhancing the output power. The small-signal measurement results closely match the simulation results, and the large-signal measurement results at the operating frequency of 40 GHz show the OP1dB is 12.9 dBm and the PAE is 7.28% at P1dB.
In Chapter 3, we design a power amplifier using the WIN 100-nm GaAs pHEMT process, operating at a center frequency of 40 GHz in the Q-Band. This power amplifier has a two-stage balanced architecture and uses a Lange coupler for power combining. We referenced previous results, which were for two single-stage power amplifiers with transistor sizes corresponding to the driver and output stages of the circuit in this chapter. Through debugging and re-simulating these two single-stage power amplifiers, we applied the findings to the design in this chapter. The measurement results show a gain of approximately 13.4 dB, OP1dB is 27.8 dBm, and the PAE is 27.7% at P1dB, measured at 40 GHz.
In Chapter 4, we design a power amplifier using the WIN 100-nm GaAs pHEMT process, operating at a center frequency of 80 GHz in the E-Band. This amplifier has a three-stage architecture. We referenced a previously fabricated single-stage power amplifier with transistor sizes corresponding to the second and third stages of the circuit in this chapter. Through debugging and re-simulating this single-stage power amplifier, we applied the findings to the design in this chapter. The measurement results show a gain of approximately 12.4 dB, OP1dB is 22.7 dBm, and the PAE is 29.4% at P1dB, measured at 80 GHz. | en_US |