| dc.description.abstract | This thesis investigates the designs of the local oscillators for the applications in X-band. In this thesis, we firstly introduce the oscillation condition, analyze the causes of phase noise and finally illustrate the circuit implemented in this thesis. In this thesis, three LO circuits were implemented in tsmcTM 0.18 μm CMOS processes. The developed LO circuits are listed as follow:
I. A Class-F Voltage Controlled Oscillator
This circuit implements a Class-F voltage-controlled oscillator with low phase noise. It uses transformer coupling to realize the fundamental, second, and third order resonant. By making the output waveform appear like a square wave, Class F operation is achieved. The measurements are listed as below, under a 0.7 V DC supply, the circuit power consumption is 9.1 ~ 10.5 mW, the operation frequency is from 10.14 to 11.45 GHz, (i.e., 12.1% tuning range). After subtracting the cable loss, the measured output power is ?1.59 ~ ?0.2 dBm, the best phase noise at 1-MHz offset frequency is -115 dBc/Hz, FOM and FOMT are -185.11 dBc/Hz and -186.79 dBc/Hz respectively, the chip area including I/O PAD is 0.99 × 0.82 mm2.
II. A dynamic body biasing technique low power consumption on Class-B/C Hybrid-Mode VCO
This circuit implements a Class B/C hybrid voltage-controlled oscillator with low power consumption. Through Class-C high current efficiency operation and forward body biasing technique, the voltage-controlled oscillator can achieve the goal of low power consumption. And PMOS auxiliary oscillation operating in Class-B to solve hard start-up problem of the Class-C oscillator. Under the DC supply of 1.1 V, the circuit power consumption is 2.5 mW, the operation frequency is from 10 to 10.7 GHz, (i.e., 6.7% tuning range). The measured output power after adding cable loss is ?5.3 ~ ?8.2 dBm, and the best phase noise at the 1-MHz offset frequency is -108.6 dBc/Hz, and the best FOM and FOMT are -184.7 dBc/Hz and -181.4 dBc/Hz respectively. The chip area including I/O PAD is 0.89 × 0.69 mm2.
III. An X-band integer-N Phase Locked Loop (PLL) with Class-F Voltage-Controlled Oscillator
This circuit uses the first designed class-F voltage-controlled oscillator to implement an integer phase-locked loop (PLL) in X-band. The circuit includes a voltage-controlled oscillator, a current mode logic divider, a differential to single buffer, TSPC dividers, full-swing buffers, phase and frequency detector, a charge pump, and a loop filter. Chapters include an introduction and analysis of each sub-circuit. The measurements are listed as, the PLL is locked from 9.63 to 10.28 GHz when reference signal is 37.64 to 40.16 MHz. The division ratio is dual-mode 256 and 260. The overall power consumption is about 46.8 mW. The chip area including the I/O PAD is 1.2 × 0.95 mm2. At the center frequency of 10 GHz, the reference spur is as low as -45 dBc and phase noise is -96.9 dBc/Hz at 1-MHz offset. The clock jitter from 10 kHz to 40 MHz (SSA instrument measurement limit) is 940 fsec. | en_US |