| dc.description.abstract | This thesis presents the design and development of three integrated circuits using the 0.18-μm CMOS process provided by Taiwan Semiconductor Manufacturing Company (tsmc?). The circuits include two wideband low-noise amplifiers (LNAs) targeting the C/X bands and a wideband receiver operating in the same frequency range.
The first chip is a wideband LNA designed using a transformer comprising gate and source degeneration inductors for input matching. This approach enhances high-frequency gain and broadens the bandwidth. A cascode structure is employed in the second stage to achieve high gain, with inductive peaking techniques used to improve gain flatness. This design optimizes power consumption, output matching, and chip area, while also flattening the gain. Measured results show a maximum gain (S21) of 13.45 dB, a 3-dB bandwidth spanning from 5.7 to 13.1 GHz, a minimum noise figure (NF) of 3.06 dB, a P1dB between -14 and -16.5 dBm, and an IIP3 ranging from -4 to -7 dBm, with a power consumption of 13.63 mW. The chip area is 1.17 × 1 mm2.
The second chip is a wideband LNA featuring a resistive feedback inverter. The first stage combines the feedback inverter with a gate-source transformer to achieve wideband input matching, while the second stage employs a cascode structure and a drain-source transformer to enhance gain flatness. The design optimizes noise matching at high frequencies, sacrificing some low-frequency performance to achieve uniform noise matching across the bandwidth. Measured results show a maximum gain (S21) of 12.01 dB, a 3-dB bandwidth from 4.5 to 12.6 GHz, a minimum noise figure (NF) of 3.59 dB, a P1dB between -10 and -15 dBm, and an IIP3 from -1 to -5 dBm, with a power consumption of 12.69 mW. The chip area is 0.92 × 0.84 mm2.
The third chip is a wideband receiver designed for the C/X band. The receiver’s front end comprises four sub-circuits: a wideband LNA (utilizing the second circuit′s design), a wideband balun with dual resonance points, a double-balanced passive mixer, and a two-stage transimpedance amplifier (TIA). This architecture enhances signal isolation, gain flatness, and reduces power consumption. Measured results show a maximum conversion gain of 29.96 dB, a 3-dB bandwidth of 4 to 11.5 GHz, a minimum double-sideband noise figure (NFdSB) of 7.3 dB, a P1dB between -24 and -26 dBm, and an IIP3 ranging from -11 to -23 dBm, with a power consumption of 25.35 mW. The chip area is 1.92 × 0.84 mm2. | en_US |