| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程研究所 | zh_TW |
| DC.creator | 陳怡廷 | zh_TW |
| DC.creator | Yi-Ting Chen | en_US |
| dc.date.accessioned | 2001-7-9T07:39:07Z | |
| dc.date.available | 2001-7-9T07:39:07Z | |
| dc.date.issued | 2001 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:444/thesis/view_etd.asp?URN=88521072 | |
| dc.contributor.department | 電機工程研究所 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 本篇論文介紹一個為內嵌式系統設計的可程式化數位信號處理器( Digital Signal Processor )的架構與資料通路( data path )。為了符合各種不同內嵌式系統的需求，於是我們提出有彈性而且低功率的數位訊號處理器。
這個可參數化的數位訊號處理器有不同獨立的參數可以設定。我們更進一步地加入一些特殊應用於通訊系統的電路給使用者選用。我們把這一種處理器稱為可參數化融合特殊應用於數位訊號基礎的處理器 ( parameterized ASIC/DSP processor )。除了特殊應用的電路外，為了增強整體的效能，我們加入高度平行化的架構稱之為雙 MAC 架構。最後，為了減少功率消耗，我們也應用了一個低功率的 MAC 單元在這顆數位訊號處理器裡。 | zh_TW |
| dc.description.abstract | This thesis introduces the architecture and data path of a programmable DSP processor designed for embedded system. To meet the various embedded system needs, a flexible and low power DSP core is proposed.
The proposed DSP processor itself is a parameterized core with several independent parameters. Furthermore, a better concept is to combine some special-purposed circuits in the parameterized DSP core for option. And we term this kind processor as parameterized ASIC/DSP processor. In addition to the special-purposed circuits, the highly degree parallelism architecture ( Dual MAC ) is used in the processor to upgrade its performance. In order to reduce the power consumption, a low power MAC unit is used in the DSP | en_US |
| DC.subject | 數位訊號處理器 | zh_TW |
| DC.subject | 資料通路 | zh_TW |
| DC.subject | data path | en_US |
| DC.subject | DSP processor | en_US |
| DC.title | 適用於通訊系統的內嵌式數位信號模組設計 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | The Data Path of Embedded DSP Architecturefor Communication Application | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |