dc.description.abstract | Digital audio coding is popular and has been applied in many areas. The conventional implementation approaches for these audio decoders can be categorized to three methods, i.e. dedicated hardware, software-based general purpose processor (GPP) and hardware/software co-design. This dissertation covers the key techniques of all these methods and brings four contributions. First, an implementation of low power and pure hardware AAC audio decoder system is presented. Based on the characteristics of each decoding block, the AAC system is partitioned into four separate modules. For the low power and low complexity considerations, architectural and algorithmic level approaches are adopted in both the individual modules and the whole system. Referring to stereo processing, a single hardware is shared for the channel pairs with the low cost consideration. The hardware operations of each module are well scheduled with high utilization of pipeline, and further the parallel processing among blocks are joined to increase the efficiency. A 48 % power savings can be reached by using the pipeline and parallel techniques of the channel pair. The proposed AAC decoder is realized in UMC 0.18 ?m 1P6M technology and operated at only 3 MHz in the worst case. The power dissipation is only 2.45 mW at the sampling frequency of 44.1KHz.
Second, due to audio applications for mobile phone and portable devices are increasingly popular. To attract consumer interest, a multi-standard design on a single device is the requirement of current audio decoder development. We present a configurable common filterbank processor (CCFP) for AC-3, MP3 and AAC audio decoder. It is used as an accelerator for general purpose processors to improve performance. All the filterbank transforms are derived to even- or odd-point IFFT flows. In the architecture, a fully pipelined approach is developed which can be configured for different operation modes. This design is synthesized using UMC 0.18 µm library and takes about 26.7K gates. It can be executed at a very low operation frequency with the range of 1.3 to 3.6 MHz. Besides, the power consumption is only 0.9 mW, 3.2 mW and 1 mW for AC-3, MP3 and AAC respectively.
Third, SoC integration platform provides the flexibility of general-purpose processors and the high performance and low power consumption of custom hardware. We present a Hardware/Software co-design method for the implementation of AAC audio decoder. This approach not only considers the characteristics of algorithms, but also provides the numerical decision for evaluation of the various approaches. The overall system is first analyzed and profiled with ARM profiler. Then the decoder system is partitioned into software part and hardware part respectively based on the property of analysis. Besides, a multi-standard audio decoder based on the SoC Hardware/Software co-design approach is also presented. It supports popular audio formats including AC-3, MP3 and AAC. By using the accelerator and the processor with cache enabled, the overall system can get more than 15x speedup compared to software-based ARM audio decoder.
Finally, we propose VLIW-aware software optimization techniques for the AAC decoding blocks on the parallel architecture core DSP (PACDSP) processor. This approach provides the flexibility for adding new extensions and solves two important issues, low power consumption and limited resources problems on DSP for portable devices. We change the traditional sequential algorithms into parallel processes and minimize the memory utilization of each block. The realized decoder can be operated at a lower frequency of only 15 MHz and needs only 27 Kbytes of program memory and 27 Kbytes of data memory. | en_US |