| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 黃宣澍 | zh_TW |
| DC.creator | Hsuan-Shu Huang | en_US |
| dc.date.accessioned | 2003-7-4T07:39:07Z | |
| dc.date.available | 2003-7-4T07:39:07Z | |
| dc.date.issued | 2003 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:444/thesis/view_etd.asp?URN=90521021 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 本論文提出一個新的以串流加密器為架構的資料加密晶片並利用替換網路來當作加強安全的第二級加密方法且在操作模式上選擇了CBC(Cipher Block Chaining mode)來作為通訊雙方同步操作的控制方法。
在設計方法上採用由下至上的階層式設計，並針對傳統替換盒(s-box)之核心函數f的選取上採用一時變設計(time-variable) 。
此晶片可為微處理器的周邊裝置，也可應用於網路相關產品上。使用者可自定8 位元的密鑰，其應用範圍可以包括即時(real-time)資料傳輸與語音通訊。
本研究之加密器利用了VHDL’92和Synplify 以及Maxplus II來設計、合成及模擬。最後使用FPGA (Field Programmable Gate Array) 來驗證其功能。其所需logic cell數量為169，最高工作頻率及資料處理量分別約為100MHz及80Mbps. | zh_TW |
| dc.description.abstract | The thesis presents a new design of stream cipher encryption chip and makes use of S.P.N.(Substitution Permutation Networks) as second stage to enhance backwards of conventional cipher. The cipher chooses CBC(Cipher Block Chaining mode) as operation mode to be synchronization control between encryption and decryption devices.
Adopting “bottom-up” design is used to improve performances. The new design is aimed at f function selection. The chip is a microprocessor peripheral device and could be useful for network devices. They use an 8-bit user-specified key to encrypt and decrypt 8-bit blocks of data.
The chip can be used in real time applications and variety of Electronic Funds Transfer applications. In order to reduce the I/O pins, the shift registers are designed as parallel process.
By making use of VHDL’92, Synplify, and Maxplus9.6 ?for designing. Synthesizing and simulating is prepared to realize the chip. Field Programmable Gate Arrays (FPGAs) are chosen as our target hardware environment and verification function with board. The design of this chip for area requires 169 logic cells. The maximum operating clock is 100 MHz and the corresponding data throughput is about 80 Mbps. | en_US |
| DC.subject | 串流加密器 | zh_TW |
| DC.subject | stream cipher | en_US |
| DC.title | 使用FPGA 實現一串流加密模組之
設計與驗證 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | A New Design and Verification ofStream Cipher Module UsingFPGA Device
| en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |