| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 黃伯任 | zh_TW |
| DC.creator | Po-Jen Huang | en_US |
| dc.date.accessioned | 2003-7-8T07:39:07Z | |
| dc.date.available | 2003-7-8T07:39:07Z | |
| dc.date.issued | 2003 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:444/thesis/view_etd.asp?URN=90521049 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 在此論文中，我們主要的研究主題是探討同步切換雜訊對訊號完整性的影響，並進而去降低雜訊的量。首先，我們將簡單的說明及討論通道建模、介面電路的雜訊來源及低電壓差動訊號標準，並簡介造成同步切換雜訊的相關因素和過去一般用來降低此雜訊的機制。根據這些知識，我們提出了輸出驅動器的電晶體順序導通的方法，藉由電流非同時流到接地端的打線來有效的降低同步切換雜訊。接著，我們利用這個原理，應用在一個符合AGTL標準的2Gbps收發器，及一個符合低電壓差動訊號標準的5Gbps收發器。此外，在不使用電流源的情況下，我們亦可以大幅的降低電晶體的尺寸及花費。並在電路內加上一個編碼器，讓電路在製程漂移的情況下，輸出的電壓準位還能維持在一定電壓範圍。
論文中，我們將實現一個符合AGTL標準的2Gbps的傳送器。此傳送器是使用tsmc018的製程且在1.8V的供應電壓下可以操作在2Gbps，另外晶片面積則為1.5x1.5mm2，模擬結果可以讓同步切換雜訊抑制在原有雜訊的一半以內。另外我們亦模擬一個符合低電壓差動訊號標準的5Gbps收發器，將同步切換雜訊抑制在50mV左右。透過這些處理，我們可以不使用電流源而有效的抑制雜訊的量，並讓輸出訊號能維持在標準的電壓準位。 | zh_TW |
| dc.description.abstract | In this thesis, our major topic is to discuss the effect of simultaneous switching noise (SSN) on signal integrity and to reduce the noise magnitude. First, we will study the channel modeling, signaling noise sources and low voltage differential signaling (LVDS) standard. We also briefly introduce the factors which causes SSN and some mechanisms to reduce the noise in the past. Basing on these considerations, we propose the orderly turn-on method of the output driver, and we apply this method in a 2Gbps transceiver of the assisted gunning transceiver logic (AGTL) standard and a 5Gbps transceiver of the LVDS standard. Without using the current source, we can further reduce the transistor size and the cost. We also invent a decoder to control the voltage level against the process variation.
A 2Gbps transmitter has been implemented in this thesis. It is compatible with the AGTL standard. Fabricated in a TSMC 0.18-um CMOS technology, the transmitter circuit operates at 2Gbps with a 1.8V power supply and the chip area is 1.5x1.5mm2. It has been approved for fabrication by the Chip Implementation Center (CIC). The simulation result shows that the SSN effects have been reduced to half of the original ones. Furthermore, we also simulate a 5Gbps transceiver of the LVDS standard and the SSN effect has been reduced to 70mV. By these methods, we can reduce the SSN effect and maintain the voltage level of output signal without using any current source. | en_US |
| DC.subject | 同步切換雜訊 | zh_TW |
| DC.subject | 低電壓差動訊號 | zh_TW |
| DC.subject | 輸出驅動器 | zh_TW |
| DC.subject | SSN | en_US |
| DC.subject | AGTL | en_US |
| DC.subject | LVDS | en_US |
| DC.subject | transmitter | en_US |
| DC.title | 抑制同步切換雜訊之高速傳輸器 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | The high-speed transmitter for simultaneous switching noise rejection | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |