博碩士論文 90521052 完整後設資料紀錄

DC 欄位 語言
DC.contributor電機工程學系zh_TW
DC.creator張用璽zh_TW
DC.creatorLong-Xi Changen_US
dc.date.accessioned2003-7-9T07:39:07Z
dc.date.available2003-7-9T07:39:07Z
dc.date.issued2003
dc.identifier.urihttp://ir.lib.ncu.edu.tw:444/thesis/view_etd.asp?URN=90521052
dc.contributor.department電機工程學系zh_TW
DC.description國立中央大學zh_TW
DC.descriptionNational Central Universityen_US
dc.description.abstract本論文的設計,主要是以中頻接收端通訊系統應用為目標。論文所包含的電路架構計有自動增益回授控制系統,和類比數位轉換器兩大部分。 在自動控制增益迴路方面,為一負回授系統,而其中可調增益放大器的增益值,將由迴路加以控制,用以穩定輸入訊號振幅大小不同變化。也因為其放大電路操作於線性放大區,所以對訊號造成的變形,影響較小,並且在輸入信號100MHz操作下可以擁有30dB的振幅增益控制範圍而輸入信號的振幅範圍是10mVpp到300mVpp振幅大小,同時為了符合現在低電壓下的操作系統,所以是在0.18um製成1.8V的操作電壓下設計,所消耗的功率為21mW。 在類比數位轉換器方面,希望能夠設計出擁有高解析度並且高速的類比數位轉換器為主,以期待能應用在Cable Modem和HDTV的使用上。在設計上類比數位轉換器是採用管線化的方式使操作速率提升。在取樣保持電路上是採用Flip-Around的方式使得在保持模式時的回授因子降到最小,以節省操作放大器的功率消耗。而在電路精確度的考量上,藉由每一位元的重合數位矯正技術,使每一級的誤差容忍度有500mV。在100MS/s的操作頻率下,這個類比數位轉換器擁有10-bit的準確度。此電路設計是在0.18um製成3.3V操作下設計的,所號功率為557mW。zh_TW
dc.description.abstractThe project of this thesis is analog front-end circuits design for IF receiver. It concludes two components – an automatic gain control system design and an analog-to-digital system design. In the automatic gain control system design, this system is a feedback closed loop control system and its gain can be controlled by this feedback closed loop system. Because of this gain control mechanism, the output of the system has constant magnitude with different input magnitude swings, and the output signal will have lower distortion. When input signal is 100MHz, the gain control range of this system is 30dB and the input signal range is from 10mVpp to 300mVpp. The technology is UMC018 process, power supply is 1.8V, and power consumption is 21mW. In the analog-to-digital converter system design, a 100MSs/s 10-bit pipelined analog-to-digital converter system is designed, and it will used in the cable modem communication system or HDTV. This converter utilizes pipelined architecture to have 100MS/s conversion rate. In sample-and-hold amplifier design, it utilizes the flip-around architecture to have best feedback closed loop factor, so the OP in the sample-and-hold amplifier will cost lower power. The coarse quantizer can tolerate 500mV comparator offset without overflow by digital error correction technique. The effect of process variation in the circuit will be estimated by Monte-Carlo simulation. The technology is TSMC018 process 3.3V CMOS model, power supply is 3.3V, and power consumption is 557mW.en_US
DC.subject中頻接收端zh_TW
DC.subject類比數位轉換器zh_TW
DC.subject自動增益控制電路zh_TW
DC.subject可變增益放大器zh_TW
DC.subject振幅峰值偵測器zh_TW
DC.subject取樣保持電路zh_TW
DC.subjectADCen_US
DC.subjectAGCen_US
DC.subjectSHAen_US
DC.subjectVGAen_US
DC.subjectpeak detectoren_US
DC.subjectcable modemen_US
DC.title適用於中頻接收端的類比前級電路設計zh_TW
dc.language.isozh-TWzh-TW
DC.titleAnalog Front-End Circuits Design for IF Receiveren_US
DC.type博碩士論文zh_TW
DC.typethesisen_US
DC.publisherNational Central Universityen_US

若有論文相關問題,請聯絡國立中央大學圖書館推廣服務組 TEL:(03)422-7151轉57407,或E-mail聯絡  - 隱私權政策聲明