dc.description.abstract | Abstract
The thesis describes various circuit designs in radio frequency transceiver for WB-CDMA and dual-band WLAN applications those are implemented in tsmc 0.35?m SiGe BiCMOS technology. Chapter one gives a brief description of the device technologies and the contents of each following chapters.
Chapter two reports a super-heterodyne receiver design for WB-CDMA applications, which contains a 1.95 GHz low noise amplifier design and a 1.95 GHz mixer design. The LNA provides approximately 20 dB gain with input/output return loss better than 10 dB, and has input P1dB of -29.5 dBm, input IP3 of -16 dBm. The mixer achieves 5.4 dB conversion loss, and has input P1dB of -3.5 dBm, input IP3 of 8.5 dBm, IF bandwidth of 500 MHz, and the isolations between RF port and LO port are better than 30 dB without except.
Chapter three reports a direct conversion receiver design for dual-band three-mode WLAN application, which contains a 2.4/5.2/5.8 GHz low noise amplifier design and a 2.4/5.2/5.8 GHz sub-harmonic mixer (SHMIX) design. In three diverse operation frequencies, the dual-band three-mode LNA provides better than those properties below without except, that are 15 dB gain with input/output return loss better than 10 dB, and has input P1dB of -24 dBm, input IP3 of -9 dBm. The dual-band three-mode SHMIX in all of the operation frequencies also achieves better than -5 dB conversion gain, and has input P1dB of -2 dBm, input IP3 of 3 dBm, IF bandwidth of 50 MHz, and the isolations among all ports are better than 35 dB.
Chapter four reports a direct conversion transceiver design for WB-CDMA application, which contains a 2.15 GHz fully differential variable gain direct conversion receiver (DCR) design, three 1.95 GHz high average power added efficiency (PAEAverage) power amplifier designs, and a 2.15 GHz quadrature phase Colpitts voltage controlled oscillator (QVCO) design. The DCR provides more than 20 dB gain with input return loss better than 7.5 dB, and has input P1dB of -29 dBm, gain controlled range of 12 dB. Three different circuit architectures are high PAEAverage PA designs are adaptive bias PA (A-PA), adaptive bias Doherty PA (AD-PA), and adaptive bias extended Doherty PA (AED-PA), respectively. The A-PA provides 13.5 dB gain with input/output return loss better than 10 dB, and has output P1dB of 13.6 dBm, output IP3 of 19 dBm, the maximum PAE of 38 %. The AD-PA provides 7 dB gain with input/output return loss better than 10 dB, and has output P1dB of 16.5 dBm, output IP3 of 14.8 dBm, the maximum PAE of 27 %. The four-way AED-PA provides 5 dB gain with input/output return loss better than 10 dB, and has output P1dB of 16.5 dBm, output IP3 of 23.6 dBm, the maximum PAE of 22 %. In contrast to the A-PA, the PAEAverage of AD-PA and four-way AED-PA have remarkably been improved of 243% and 317%, respectively. Finally, the QVCO has tuning range of 160 MHz with tuning gain of 48.5 MHz/V, output power of -10 dBm, and the phase noise approximate at -85 dBc/Hz on 100 kHz offset frequency. | en_US |