| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 王妍尹 | zh_TW |
| DC.creator | Yen-Yin Wang | en_US |
| dc.date.accessioned | 2004-7-13T07:39:07Z | |
| dc.date.available | 2004-7-13T07:39:07Z | |
| dc.date.issued | 2004 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:444/thesis/view_etd.asp?URN=91521021 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 近年來，由於多媒體之應用，資料傳輸量愈來愈大，高速序列已達到每
秒兆位元的速度，因其低廉之價格故廣為應用。
在本論文中，首先我們比較分析兩種在接收端常用之高速資料回復系統:
超取樣方式以及鎖相迴路方式來完成資料回復。在接收端的實現方面可分為前
端的取樣電路以及資料回復電路，除了實現其電路架構外更近一步對其做理論
分析。前端的取樣電路對操作在8Gbp 的差動信號對做接收放大然後信號再經
過資料回復電路做處理。而由於我們用超取樣之方式實現全數位之資料回復電
路架構，因此一些重要的效能及設計參數都被分析及公式化使不同的設計參數
可以符合不同的系統規格。此外對整個資料回復電路做一套影響系統效能的雜
訊以及錯誤率分析以及將影響系統效能的因素參數化。最後結合所有的設計參
數以及電路架構我們建構出一個模組產生器。藉著模組產生器，使得整個資料
回復電路透過參數化的過程使設計具有彈性並自動產生出可合成之Verilog
程式。 | zh_TW |
| dc.description.abstract | Due to the increasing applications of multimedia in recent years, the
requirement of data bandwidth has been increased. High speed serial link that
achieves Gbps has the advantage of low cost and thus become popular.
First, we compare and analyze two types of data recovery systems usually used
in high speed serial link receiver. One is the PLL-based clock extraction and the
other is the oversampling phase-picking. In this thesis, an input sampler and the
oversampling based data recovery circuits and its theoretical analysis are proposed
for Gbps receiver. Second, an input sampler that receives differential signal of
8Gbps and amplify the differential signal to become digital signal is proposed.
Third, we adopt an oversampling phase-picking method to realize an all digital data
recovery circuit. Several key performance and design parameters are analyzed and
formulated, therefore, different specifications can be met with different design
parameters. Besides, we derive a set of jitter and BER analysis equation of the
oversampling method. Moreover, we parameterize the factors that influence the
performance of the system. Finally, by combining all the design parameters and the
architecture, we make a module generator of the oversampling data recovery circuit.
By utilizing the proposed module generator we make the design of data recovery
circuit more flexible and can generate the synthesizable Verilog code automatically. | en_US |
| DC.subject | 模組產生器 | zh_TW |
| DC.subject | 資料回復 | zh_TW |
| DC.subject | 超取樣 | zh_TW |
| DC.subject | module generat | en_US |
| DC.subject | CDR | en_US |
| DC.subject | oversampling | en_US |
| DC.subject | data recovery | en_US |
| DC.title | 串列式傳輸接收器之設計與實現 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Serial Link Receiver Design and Implementation | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |