| dc.description.abstract | Power dissipation and area cost are two major design concerns of the ternary content addressable memory (TCAM). This thesis presents a 10T static cell and a low-power design methodology for TCAMs. The proposed 10T cell makes a static TCAM be able to be implemented with very low area cost. Compared with a typical 9T static binary cell, only one additional transistor is needed to realize a static ternary cell. Experimental results show that the proposed 10T cell only need about 13.83um2. A low-power design technique is also proposed to reduce the Search power by dividing the match line of a word into multiple cascaded small match lines. Simulation results show that for a 32 x 64 TCAM, about 10%~70% Search power reduction can be achieved if the ratio of empty segments is higher than 37.5% and the segment width is 8.
On the other hand, testing TCAMs is very complicated due to their special structure. In this thesis we develop functional fault models based on physical defects, such as short defects, open defects, transistor stuck-on defects, and transistor stuck-off defects. We also propose a March-like test algorithm for TCAMs based on the proposed functional faults. The test algorithm only requires basic TCAM operations, Write, Search, and Erase, and the test response can be observed entirely from the single-bit Hit output. The test algorithm requires 4N+2W Search operations, 4N Write operations, and 4N Erase operations to cover 100% target comparison faults for an N x W-bit TCAM. | en_US |