| dc.description.abstract | As VLSI technology advances into the nanometer era, the power integrity problem is becoming one of the most critical issues that limit design performance. IR-drop and simultaneous switching noise (SSN) are two major power supply noises (PSNs) causing power integrity problems. Because these two noises are highly dependent on the magnitude and slope of supply currents, accurate supply current waveforms are required for precise analysis.
Traditionally, accurate supply current waveforms can only be obtained using the transistor-level circuit simulation. Therefore, in the present design flow, a power integrity check is performed mostly in late design stages. This approach may be impractical for large designs because simulating the entire design at the transistor level requires great computational resources. If a power integrity problem is identified, designers often increase the width of the supply lines or add decoupling capacitors to reduce the IR-drops. However, if the supply current waveforms can be obtained in early design stages, more efficient IR-drop reduction technologies can be used to reduce the power supply noise, such as re-synthesis and power-gating.
In the present design flow, supply current waveforms are not easily obtained in early design stages because of two major reasons. The first reason is the lack of supply voltage information at the front-end design level. All internal voltages are viewed as logic-1 and logic-0 at the RT (Register Transfer)-level. Designers only consider the functional correctness of designs and ignore the IR-drop effects. At the gate level, more information is available, such as the supply voltage and the average power of each standard gate. However, this power information is inadequate in estimating IR-drops because it cannot provide the slope and maximum amplitude of the supply current for IR-drop analysis.
The second reason is the lack of dynamic changes on the power information under different supply noises. In the conventional IR-drop analysis, power girds are modeled as an RLC network, and the switching currents are modeled as simple current sources. These current sources are obtained by simulating switching circuits with ideal supply voltages. However, the supply current waveforms with the supply noises are different, compared to ideal ones. Extra errors may occur if the ideal current waveform is used to estimate the situations under supply noises.
This dissertation proposes several front-end supply current waveform modeling techniques to support the IR-drop at early design stages analysis. For gate-level designs, an analytical current model is proposed [33] [34], which uses standard library information to estimate supply current waveforms. The library adjustment method under supply noises is also proposed [35] [36] for more accurate estimation of real supply noises. For functional-level analysis, an improved macro-level current model is proposed [37] [38] to provide the essential current information. The waveform transformation method also proposed to modify the generated current waveforms to reflect the supply noise effects [38]. If these techniques are integrated in the present design flow, power integrity checks can be performed at early design stages to prevent IR-drop issues.
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