| dc.description.abstract | Increases of chip operation frequency and transmission bandwidth result in a great demands for multi-GHz clocking. However the frequency of a single clocking is limited due to signal reflection, coupling, and supply bounce. Therefore, multi-phases clocking technique is developed to improve signal integrity and reliability. It uses N-phases clocking to replace single high frequency clocking, and can reduce frequency to 1/N of single clocking frequency. However, there is a challenge to the distribution of multi-phases clocking. The clocking routing increases the area overhead and timing uncertainty.
Therefore, we propose a novel architecture to improve timing performance and reduce routing area. This architecture includes a ring-oscillator-based PLL, phase blenders, and adaptive quadrature clock generator. Although the PLL theory has been well developed, we derive practical and useful equations to estimate system parameters. The multi-phases clocking is generated by PLL and delivered by phase blenders, which has been proposed to average phase error. Because this architecture only delivers 1/4 numbers of phases on clock distribution, routing area and power consumption of clock buffers is decreased.
Finally, the adaptive quadrature clock generators are employed in the global sub-module circuits. This circuit regenerates quadrature phases clocking from a single clocking and it has been improved to wider operation frequency range due to our feedback design. Two PLLs are implemented in tsmc 0.18μm 1P4M CMOS process and UMC 0.13μm 1P8M CMOS process, and the proposed multi-phases distribution architecture is designed in UMC 0.13μm 1P8M CMOS process. | en_US |