| dc.description.abstract | Abstract
The thesis investigated the analysis, design and implementation of linear compensation power amplifiers with silicon-based technologies for W-CDMA, WLAN 802.11a applications. The power amplifiers were implemented in tsmc 0.35?m SiGe BiCMOS and 0.18?m CMOS technologies.
The brief description of the related researches is given in the chapter one and the contents of each following chapters.
In the Chapter two the specifications and the operation class of power amplifier are presented.
In the Chapter three, I report a linear power amplifier with open adaptive collector biasing design for W-CDMA applications. The size effect of linearizer is investigated to improve linearity. The impedance ratio between the bias circuit and power stage is optimized at the factor of 3. Another compensated mechanism is provided by the drain-gate connected MOS diode. The diode feedback technique provides a supplement RF current in the higher power level which further enhances the linearity of the amplifier. The circuit was implemented with tsmc SiGe BiCMOS technology. This PA provides a 13.5dB gain with input or output return loss better than 10dB, and has output P1dB of 18.6dBm; output IP3 of 27.2dBm, the maximum PAE of 31.2 %.
Chapter four reports a high linearity power amplifier for W-CDMA applications. Two different linearization architectures, Predistortion (PD) and Feedforward are studied. A simple circuit of variable gain predistorter (APD) was implemented with tsmc SiGe BiCMOS technology. The APD amplifier provides a 7.8dB gain with input better than 10dB, output return loss is 7dB and has output P1dB of 17.9dBm, output IP3 of 30dBm at Vbep=0.9V, the maximum PAE of 37%. A simple differential amplifier using feedforward technique was implemented on a single chip by tsmc SiGe BiCMOS technology. The bias point and device size ratio of differential amplifier should be carefully chosen to get proper third order nonlinearity for the IM3 cancellation. The feedforward amplifier provides a 7.06dB gain with input better than 16dB, output return loss is 8.5dB and has output P1dB of 14.4dBm, and output IP3 of 31dBm, the maximum PAE of 24.5 %.
Chapter five reports a high average efficiency power amplifier for W-CDMA and WLAN applications. Doherty amplifier and DC-DC converter amplifiers are investigated. The Doherty amplifier was implemented with tsmc CMOS technology, which is provided a 6.5dB gain with input better than 16dB, output return loss is 3dB and has output P1dB of 20dBm, output IP3 of 31dBm, the PAE of 24.5 %. The DC-DC converter amplifier was implemented by tsmc SiGe BiCMOS technology, which is provided a 9.5dB gain with input better than 18dB, output return loss is 5dB and has output P1dB of 16.8dBm, output IP3 of 30dBm, the maximum PAE of 42 %. | en_US |