| dc.description.abstract | In SOC system design using nano scale CMOS process, it is difficult to design interconnects for low power and high speed. It is because modules may use global interconnects with length up to 5000mm to exchange signals. Besides, 30% of the chip’’s dynamic power was consumed by interconnects. In this thesis, we first describe the importance of wires in the future nano scale process and the trend of interconnect link circuit and from designer’s point of view.
Therefore, we propose two novel schemes to improve the power and speed of interconnect links: current sensing technique and parallel to serial link circuit. First, we propose a serial link technique to reduce power consumption without decreasing throughout. Parallel to serial links has low complexity in routing area and save power consumption up to 60% than optimal repeater insertion method. Besides, we also propose current sensing technique for long interconnects. The advantages of current sensing techniques are: First, current sensing provides suitable impedance in receiver side to match the interconnect impedance which provides higher bandwidth in signal transmission. Second, current sensing amplifier is more suitable than voltage sensing in parallel to serial technology.
Finally, we develop a power model of interconnect link. According to technology parameter, data activity, and interconnect length, power model will help to decide the exact interconnect parameters to satisfy the performance requirements. Finally, we implement two chips in tsmc 130nm and UMC 130nm to show the performance which data rate can up to 5Gbps. | en_US |