| dc.description.abstract | Power dissipation of complex digital circuits is often estimated by using power modeling approaches. The usage of this kind of approaches does not require any detailed information of circuits. Therefore, it can be used to estimate the power dissipation of the circuits in very high abstract level. In current approaches, power-model based power estimation methods seem to be more suitable for SOC designs to quickly provide the corresponding power consumption for a given set of input vectors. However, there are still many difficulties to apply existing power models to SOC designs. In addition, a typical system often consists of many blocks with quite different properties, which require different approaches to build their power models. Therefore, in this dissertation, we focus on developing the corresponding high-level power modeling methodologies for each block in SOC designs. These IP blocks can be roughly classified into random logic blocks with combinational and sequential circuits, embedded memory blocks and processor blocks.
For random logic blocks with combinational and sequential circuits, we focus on developing a novel power modeling approach using neural network to estimate the power dissipation on high level. In our approach, the multi-layer feed-forward neural network is used for modeling combinational circuits and multi-layer recurrent neural network is used for sequential circuits. Experimental results on ISCAS’85, ISCAS’89 benchmark circuits and some real designs show that the developed power models achieve good accuracy 4.72% and 4.19% for both combinational and sequential circuits, respectively.
Embedded memories have been used extensively in modern SOC designs. In order to estimate the power consumption of the entire design correctly, an accurate memory power model is needed. However, the memory power model commonly used in commercial EDA tools is too simple to estimate the power consumption accurately. In this dissertation, we develop two methods to improve the accuracy of memory power estimation. Our enhanced memory power model can consider not only the operation mode of memory access, but also the address switching effects with scaling capability. The developed approach is very useful to be combined with the memory compiler to generate accurate power model for any specified memory size without extra characterization costs. Then the developed dummy modular approach can link our enhanced memory power model into the existing power estimation flow smoothly. The experimental results have shown that the average error of our memory power model is only less than 5%.
For micro-processor circuits, we develop a new instruction-level energy modeling approach for pipelined Very Large Instruction Word (VLIW) DSPs. The developed approach can take care of both the base energy cost of each instruction and the additional energy cost of consecutive instructions in each pipeline stage. Therefore, the power estimation can be much closer to the real pipelined behavior since the pipeline issue had been considered. The overall power estimation procedure can be separated into two phases: energy extraction phase and model re-construction phase. The experimental results have shown that the average error of our approach is less than 3% compared to gate-level power simulation. | en_US |