| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 蔡玉章 | zh_TW |
| DC.creator | Yu-Chang Tsai | en_US |
| dc.date.accessioned | 2007-7-16T07:39:07Z | |
| dc.date.available | 2007-7-16T07:39:07Z | |
| dc.date.issued | 2007 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:444/thesis/view_etd.asp?URN=945201025 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 在最近幾年由於網路和電腦運算速度的快速發展下，電子業興起了一股朝向資料傳輸和高速串列資料通訊研究的潮流。從PCI 1.0演進至目前的PCI- Express，正說明了在高資料量傳輸時的傳統平行介面技術逐漸變成由串列傳輸的介面技術所取代。在本論文中實現了一個低抖動的自我校準鎖相迴路並應用於10Gbps晶片系統傳輸鏈，此鎖相迴路用來提供時脈訊號給serializer、deserializer等電路，來做為晶片內部時脈同步的訊號。
本論文提出之低抖動自我校準鎖相迴路可以產生2.5GHz八個相位的輸出頻率，並且提供給整個系統所需的時脈訊號，且此鎖相迴路使用自我校準的機制，因此鎖相迴路可以在製程、電壓或溫度的飄移下都鎖定在2.5GHz的頻率，並且使用多頻帶的電壓控制振盪器來降低其KVCO，因此也降低雜訊對電壓控制振盪器的影響。本晶片以TSMC 0.13um 1P8M CMOS製程來實現，工作電壓為1.2V且當鎖相迴路的輸出頻率為2.5GHz時，其功率消耗為21mW。當此提出的鎖相迴路輸入時脈訊號抖動為20ps(p-p)時，其輸出最大時脈抖動為18.55ps(p-p)。當晶片包含I/O pad時，晶片總面積為0.7mm^2，而核心部分的面積為0.08mm^2。 | zh_TW |
| dc.description.abstract | Under the development of the network and computer operated speed in recent years, a trend of data transmission and studying at high-speed serial communication is growing. It is pointed out that the high-speed serial link interface is replacing gradually the conventional parallel bus interface in the large data transmission by the development of PCI bus from PCI 1.0 PCI-Express. The thesis is implemented a low jitter Self-Calibration PLL for 10Gbps SoC transmission links application. The PLL provides clock signal for serializer and deserializer. It provides synchronous clock for the 10Gbps SoC transmission links.
The thesis proposed Self-Calibration PLL generates 2.5GHz 8-phase output frequency. It provides the clock signal for the system. The PLL use Self-Calibration technique thus it can lock at 2.5GHz output frequency for process, voltage and temperature variations. And it use Multi-Band VCO to degrade the KVCO. So it degrades the noise effect of the VCO. The test chip is implemented in TSMC 0.13um 1P8M CMOS technology. It works at power supply 1.2V with 21mW power consumption, and the PLL output frequency is 2.5GHz. The maximum output jitter is 18.55ps(p-p) with input clock jitter 20ps(p-p) of the proposed PLL. The total chip area is 0.7mm^2 with I/O pads, and the core area is 0.08mm^2. | en_US |
| DC.subject | 多頻帶電壓控制振盪器 | zh_TW |
| DC.subject | 鎖相迴路 | zh_TW |
| DC.subject | 自我校準 | zh_TW |
| DC.subject | 低抖動 | zh_TW |
| DC.subject | low jitter | en_US |
| DC.subject | Multi-Band VCO | en_US |
| DC.subject | Self-Calibration | en_US |
| DC.subject | PLL | en_US |
| DC.title | 應用於10Gbps晶片系統傳輸鏈之低抖動自我校準鎖相迴路設計 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Design of Low Jitter Self-Calibration PLL for 10Gbps SoC Transmission Links Application | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |