| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 陳光亮 | zh_TW |
| DC.creator | Gwong-Liang Chen | en_US |
| dc.date.accessioned | 2007-7-11T07:39:07Z | |
| dc.date.available | 2007-7-11T07:39:07Z | |
| dc.date.issued | 2007 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:444/thesis/view_etd.asp?URN=945201053 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 在此篇論文中，目的在於改善本研究室已開發前幾代單電子/電洞電晶體元件之缺點。提升元件之良率與特性，進一步探討量子傳輸效應。首先，將高摻雜物以離子佈值的方式植入複晶矽層中。在之後的高溫熱氧化形成鍺量子點的同時，摻雜物會經由擴散的方式移動至穿隧氧化物旁，形成自我對準至量子點的源∕汲極電極。用此方法可避免在定義完閘極後才離子佈值所衍生的問題，包括源∕汲極會因為閘極在電子束微影對準上之誤差而不具對稱性，導致有寄生金氧半場效電晶體的非理想效應存在。
使用上述之方法，再藉由電子束微影、氮化矽對複晶矽具有乾蝕刻高選擇比之技術，搭配製程的設計，本論文成功製作出源、汲與閘極皆能自我對準至鍺量子點地點接觸式之高溫單電子/單電洞電晶體。整體元件的製程技術含鍺量子點的形成(經完全氧化矽鍺奈米細線以形成單一顆小於10nm的鍺量子點於通道中)完全與CMOS製程相容，並且製程簡易、再現性高。在適當的偏壓下，由於庫倫阻斷的現象，使得在室溫下電壓-電流曲線即可呈現週期性震盪，且峰谷值比可高達500以上。本論文成功地提升單電子電晶體之Ion/Ioff、切換速度和降低功率消耗，並藉由非對稱穿隧氧化層之電流特性探討載子在量子點中的穿隧過程。 | zh_TW |
| dc.description.abstract | The main purpose of this thesis is to solve the shortages of single electron/hole transistors previously fabricated in our laboratory. To improve the yield and electrical characteristics of these devices, we can get the chance to understand the quantum confinement effect in detail. First, we incorporated high concentration dopants into poly-silicon layer using ion implantation. Theses dopants will diffuse to adjacent SiO2 barrier during the subsequent oxidation process, which is used to generate a single Ge QD, to form the self-aligned source/drain electrodes to the QD. This method can avoid the misalignment issues resulting from ion implantation process after gate electrode definition. Such as the asymmetrical source/drain electrodes because of the misalignment for electron beam lithography (EBL) resulting in the non-ideal effect of parasitic MOSFET.
We have successfully fabricated the high temperature Ge quantum-point-contact SETs/SHTs with self-aligned source/drain electrodes using EBL and Si3N4/Si high selectivity plasma etching technology. The key process for Ge-QD SHTs with self-aligned electrodes includes the formation of Ge QD (one Ge QD smaller than 10 nm embedded in channel after fully oxidizing the SiGe nanowire), high etching selectivity between Si3N4 to Si and SiO2 to Si, EBL patterning, and device integration. The fabricated Ge-QD SHTs display homogeneous current oscillations at room temperature owing to Coulomb blockade effect. In particular, peak-to-valley current ratio is up to 500, and the background current (as low as 10-12 A - 10-13 A) doesn’t increase with applied gate voltage. This indicated that gate-induced tunneling barrier lowering is significantly suppressed owing to the self-aligned process. This thesis successfully improve the Ion/Ioff、switching speed and power consumption. Besides, we have experimentally studied the carrier quantum transport through the Ge QD using asymmetrical tunneling barriers device. | en_US |
| DC.subject | 自我對準電極 | zh_TW |
| DC.subject | 庫倫阻斷 | zh_TW |
| DC.subject | 單電子電晶體 | zh_TW |
| DC.subject | 量子點 | zh_TW |
| DC.subject | 鍺 | zh_TW |
| DC.subject | single electron transistor | en_US |
| DC.subject | germanium | en_US |
| DC.subject | Coulomb blockade | en_US |
| DC.subject | self-aligned electrodes | en_US |
| DC.subject | quantum dot | en_US |
| DC.title | 具有自我對準電極鍺量子點單電洞電晶體之製作與物理特性研究 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Germanium QD Single Hole Transistor with self-aligned electrodes – device fabrication and physics study | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |